@@ -216,7 +216,7 @@ static void per_pll_config(void)
;
}
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
{
u32 clkmode, clksel, div_m2;
@@ -234,7 +234,7 @@ static void ddr_pll_config(void)
;
clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+ clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
writel(clksel, &cmwkup->clkseldpllddr);
div_m2 = div_m2 & CLK_DIV_SEL;
@@ -268,7 +268,6 @@ void pll_init()
mpu_pll_config();
core_pll_config();
per_pll_config();
- ddr_pll_config();
/* Enable the required interconnect clocks */
enable_interface_clocks();
@@ -21,6 +21,7 @@
#include <asm/arch/ddr_defs.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
@@ -150,6 +151,7 @@ void config_ddr(short ddr_type)
enable_emif_clocks();
if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+ ddr_pll_config(266);
config_vtp();
config_cmd_ctrl(&ddr2_cmd_ctrl_data);
@@ -30,4 +30,5 @@ int print_cpuinfo(void);
u32 get_device_type(void);
void setup_clocks_for_console(void);
+void ddr_pll_config(unsigned int ddrpll_M);
#endif
Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com> --- arch/arm/cpu/armv7/am33xx/clock.c | 5 ++--- arch/arm/cpu/armv7/am33xx/emif4.c | 2 ++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + 3 files changed, 5 insertions(+), 3 deletions(-)