From patchwork Mon Apr 2 12:57:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 150152 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B43B3B704B for ; Mon, 2 Apr 2012 23:03:57 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C8A4280A5; Mon, 2 Apr 2012 15:03:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id h7-4QO51DIjR; Mon, 2 Apr 2012 15:03:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EAA7E28094; Mon, 2 Apr 2012 15:03:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E156C28094 for ; Mon, 2 Apr 2012 15:03:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hz1H3ECn-ffg for ; Mon, 2 Apr 2012 15:03:46 +0200 (CEST) X-Greylist: delayed 338 seconds by postgrey-1.27 at theia; Mon, 02 Apr 2012 15:03:44 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by theia.denx.de (Postfix) with ESMTPS id 5B32C28085 for ; Mon, 2 Apr 2012 15:03:44 +0200 (CEST) Received: by wibhm17 with SMTP id hm17so2437021wib.9 for ; Mon, 02 Apr 2012 06:03:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=kViKom4lkkBsos0f1HZC9cc3vwT04emc84Ha+pwOVzo=; b=QNyUx2NmWbHACaVG2YEr/qEsgEh9G9mDbFSqaeOWwkqj+Kn+eoRKDaWSIJzSxWvTAl H6pH6tjj6d2Z2f6LvLeTk9wVkk4N7N5uHnQpqFRRDAhGcaSRMDuK1F1fkyA2WLTI43Z7 lff/5OyoVSK/+2f7UVxSY5wvoVjLQp6VpA5YT7LjJUxxXYq+eFlNT9J9ER5bd4SUGMAP iaGnadr3nVwl8ssPKf4GMpKOthI5OQLg6+nPAj9FXKbSu7zJDAqSqz30+7LCsLwU/s02 lf8Ee1anmvdlGdW2QBxyLTM0jkrd8ON0HBxASQ6eG8VvCIYwzNMmpYhQD2sLxVS8W+dj Aj9Q== Received: by 10.180.101.8 with SMTP id fc8mr24890083wib.12.1333371485911; Mon, 02 Apr 2012 05:58:05 -0700 (PDT) Received: from pc000853.sas.sys.sphairon.com (dslb-178-005-083-238.pools.arcor-ip.net. [178.5.83.238]) by mx.google.com with ESMTPS id o2sm54936329wiv.11.2012.04.02.05.58.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 02 Apr 2012 05:58:05 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Date: Mon, 2 Apr 2012 14:57:55 +0200 Message-Id: <1333371476-30691-3-git-send-email-daniel.schwierzeck@googlemail.com> X-Mailer: git-send-email 1.7.9.4 In-Reply-To: <1333371476-30691-1-git-send-email-daniel.schwierzeck@googlemail.com> References: <1333371476-30691-1-git-send-email-daniel.schwierzeck@googlemail.com> Cc: Marek Vasut , Shinya Kuribayashi Subject: [U-Boot] [PATCH 2/3] MIPS: fix inconsistency in config option for cache operation mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable(). Fix this to avoid inconsistencies if someone wants to disable and enable D-caches. Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 5ce0ec4..e683e8b 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -30,6 +30,10 @@ #include #include +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + #define RA t8 /* @@ -224,7 +228,7 @@ LEAF(dcache_enable) mfc0 t0, CP0_CONFIG ori t0, CONF_CM_CMASK xori t0, CONF_CM_CMASK - ori t0, CONF_CM_CACHABLE_NONCOHERENT + ori t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG jr ra END(dcache_enable)