| Message ID | 1331693804-2348-1-git-send-email-festevam@gmail.com |
|---|---|
| State | Changes Requested |
| Headers | show |
>-----Original Message----- >From: Fabio Estevam [mailto:festevam@gmail.com] >Sent: Wednesday, March 14, 2012 10:57 AM >To: u-boot@lists.denx.de >Cc: sbabic@denx.de; eric.nelson@boundarydevices.com; >dirk.behme@de.bosch.com; Liu Hui-R64343; Estevam Fabio-R49496 >Subject: [PATCH v3] mx6: Read silicon revision from register > >Instead of hardcoding the mx6 silicon revision, read it in run-time. > >Also, besides the silicon version also print the mx6 variant type: quad, >dual/solo or solo-lite. > >Tested on a mx6qsabrelite, where it shows: > >CPU: Freescale i.MX6Q rev1.0 at 792 MHz > >Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> >--- >Changes since v2: >- Read both chip variant and chip silicon version from anatop >- Create a struct for accessing the anatop registers Changes since v1: >- Fix typo on Subject > arch/arm/cpu/armv7/imx-common/cpu.c | 19 +++++++++++++++++-- > arch/arm/cpu/armv7/mx6/soc.c | 8 +++++++- > arch/arm/include/asm/arch-mx6/imx-regs.h | 5 +++++ > 3 files changed, 29 insertions(+), 3 deletions(-) [...] >diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h >b/arch/arm/include/asm/arch-mx6/imx-regs.h >index 5ba5f39..9644807 100644 >--- a/arch/arm/include/asm/arch-mx6/imx-regs.h >+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h >@@ -294,5 +294,10 @@ struct aipstz_regs { > u32 opacr4; > }; > >+struct anatop_regs { >+ u8 rsvd[0x260]; /* To be completed as needed */ >+ u32 siliconid; >+}; I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg. ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts: ANADIG in CCM: for example: PLL/PFD, ANAREG in power: internal analog regulator, power tree. ANAUSB in usb: for usb vbus dection, charge, etc. ANAMISC: misc feature, only one register now for the Chip Silicon Version So the siliconid is in the last register. Jason Liu
On Wed, Mar 14, 2012 at 3:09 AM, Liu Hui-R64343 <r64343@freescale.com> wrote: > I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg. > > ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts: > > ANADIG in CCM: for example: PLL/PFD, > ANAREG in power: internal analog regulator, power tree. > ANAUSB in usb: for usb vbus dection, charge, etc. > ANAMISC: misc feature, only one register now for the Chip Silicon Version > > So the siliconid is in the last register. In the mx6 reference manual version I have I cannot find all the fields you mentioned. Can you send me offline the anatop register layout so that I can complete this structure?
Hi Fabio, On 03/14/2012 11:24 AM, Fabio Estevam wrote: > On Wed, Mar 14, 2012 at 3:09 AM, Liu Hui-R64343 <r64343@freescale.com> wrote: > >> I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg. >> >> ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts: >> >> ANADIG in CCM: for example: PLL/PFD, >> ANAREG in power: internal analog regulator, power tree. >> ANAUSB in usb: for usb vbus dection, charge, etc. >> ANAMISC: misc feature, only one register now for the Chip Silicon Version >> >> So the siliconid is in the last register. > > In the mx6 reference manual version I have I cannot find all the > fields you mentioned. > > Can you send me offline the anatop register layout so that I can > complete this structure? I think "arch/arm/mach-mx6/regs-anadig.h" from Freescale's 2.6.38 kernel tree does define the register layout. Do you have that file? Wolfgang.
On 03/14/2012 05:10 AM, Wolfgang Grandegger wrote: > Hi Fabio, > > On 03/14/2012 11:24 AM, Fabio Estevam wrote: >> On Wed, Mar 14, 2012 at 3:09 AM, Liu Hui-R64343<r64343@freescale.com> wrote: >> >>> I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg. >>> >>> ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts: >>> >>> ANADIG in CCM: for example: PLL/PFD, >>> ANAREG in power: internal analog regulator, power tree. >>> ANAUSB in usb: for usb vbus dection, charge, etc. >>> ANAMISC: misc feature, only one register now for the Chip Silicon Version >>> >>> So the siliconid is in the last register. >> >> In the mx6 reference manual version I have I cannot find all the >> fields you mentioned. >> >> Can you send me offline the anatop register layout so that I can >> complete this structure? > > I think "arch/arm/mach-mx6/regs-anadig.h" from Freescale's 2.6.38 kernel > tree does define the register layout. Do you have that file? > If not, you can grab it from here: http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=blob;f=include/asm-arm/arch-mx6/regs-anadig.h;h=581064b876244c65b3a0c82bf14a2f3639864b9f;hb=imx_v2009.08_11.11.01
diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 6d7486b..6ced943 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -64,13 +64,28 @@ static char *get_reset_cause(void) } #if defined(CONFIG_DISPLAY_CPUINFO) + +static char *get_mx6_type(u32 mx6type) +{ + switch (mx6type) { + case 0x63: + return "Q"; /* Quad-core version of the mx6 */ + case 0x61: + return "DS"; /* Dual/Solo version of the mx6 */ + case 0x60: + return "SL"; /* Solo-Lite version of the mx6 */ + default: + return "unknown"; + } +} + int print_cpuinfo(void) { u32 cpurev; cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", - (cpurev & 0xFF000) >> 12, + printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", + get_mx6_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 2ac74b5..a9772ca 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -32,7 +32,13 @@ u32 get_cpu_rev(void) { - int system_rev = 0x61000 | CHIP_REV_1_0; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + int reg = readl(&anatop->siliconid); + + /* Read mx6 variant: quad, dual or solo */ + int system_rev = (reg >> 4) & 0xFF000; + /* Read mx6 silicon revision */ + system_rev |= (reg & 0xFF) + 0x10; return system_rev; } diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5ba5f39..9644807 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -294,5 +294,10 @@ struct aipstz_regs { u32 opacr4; }; +struct anatop_regs { + u8 rsvd[0x260]; /* To be completed as needed */ + u32 siliconid; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version also print the mx6 variant type: quad, dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- Changes since v2: - Read both chip variant and chip silicon version from anatop - Create a struct for accessing the anatop registers Changes since v1: - Fix typo on Subject arch/arm/cpu/armv7/imx-common/cpu.c | 19 +++++++++++++++++-- arch/arm/cpu/armv7/mx6/soc.c | 8 +++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 5 +++++ 3 files changed, 29 insertions(+), 3 deletions(-)