From patchwork Fri Feb 3 16:05:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 139411 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 414A2104792 for ; Sat, 4 Feb 2012 03:06:36 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFF662810B; Fri, 3 Feb 2012 17:06:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c+J-VSVtvpsj; Fri, 3 Feb 2012 17:06:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7572028100; Fri, 3 Feb 2012 17:06:26 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C0CE280F5 for ; Fri, 3 Feb 2012 17:06:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XrmVK2JbDyY2 for ; Fri, 3 Feb 2012 17:06:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gx0-f172.google.com (mail-gx0-f172.google.com [209.85.161.172]) by theia.denx.de (Postfix) with ESMTPS id 2CA9A2809A for ; Fri, 3 Feb 2012 17:06:21 +0100 (CET) Received: by ggnq2 with SMTP id q2so1916800ggn.3 for ; Fri, 03 Feb 2012 08:06:20 -0800 (PST) Received: by 10.50.140.105 with SMTP id rf9mr13926734igb.24.1328285180410; Fri, 03 Feb 2012 08:06:20 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id g34sm11915981ibk.10.2012.02.03.08.06.16 (version=SSLv3 cipher=OTHER); Fri, 03 Feb 2012 08:06:19 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Date: Fri, 3 Feb 2012 21:35:54 +0530 Message-Id: <1328285157-23780-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1328285157-23780-1-git-send-email-chander.kashyap@linaro.org> References: <1328285157-23780-1-git-send-email-chander.kashyap@linaro.org> Cc: linaro-dev@lists.linaro.org, bjlee@samsung.com, patches@linaro.org, mk7.kang@samsung.com, samsung@lists.linaro.org Subject: [U-Boot] [PATCH v8 1/4] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap --- Changes for v2: - None Changes for v3: - None Changes for V4: - Added CONFIG_SYS_CLK_FREQ to trats.h Changes for v5: - None Changes for v6: - None Changes for v7: - None Changes for v8: - None arch/arm/cpu/armv7/exynos/clock.c | 6 +----- include/configs/s5pc210_universal.h | 1 + include/configs/trats.h | 1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0c199cd..4d92c53 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_SYS_CLK_FREQ_C210 -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#endif - /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ_C210; + freq = CONFIG_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index be000cb..8286680 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -49,6 +49,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG diff --git a/include/configs/trats.h b/include/configs/trats.h index acb3241..10f11d9 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -49,6 +49,7 @@ /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG