From patchwork Thu Dec 22 10:52:45 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 132811 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 67C68B714B for ; Thu, 22 Dec 2011 21:53:57 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BE0522812D; Thu, 22 Dec 2011 11:53:52 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id X-4w7eBKnqGB; Thu, 22 Dec 2011 11:53:52 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CD5462813F; Thu, 22 Dec 2011 11:53:38 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4D25B2811C for ; Thu, 22 Dec 2011 11:53:35 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gBWntmAv-+OB for ; Thu, 22 Dec 2011 11:53:34 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gx0-f172.google.com (mail-gx0-f172.google.com [209.85.161.172]) by theia.denx.de (Postfix) with ESMTPS id CEC4B2812D for ; Thu, 22 Dec 2011 11:53:29 +0100 (CET) Received: by mail-gx0-f172.google.com with SMTP id k5so5877558ggn.3 for ; Thu, 22 Dec 2011 02:53:29 -0800 (PST) Received: by 10.50.191.225 with SMTP id hb1mr8198930igc.17.1324551209205; Thu, 22 Dec 2011 02:53:29 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f32sm24601659ibf.9.2011.12.22.02.53.25 (version=SSLv3 cipher=OTHER); Thu, 22 Dec 2011 02:53:28 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Date: Thu, 22 Dec 2011 16:22:45 +0530 Message-Id: <1324551168-1202-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1324551168-1202-1-git-send-email-chander.kashyap@linaro.org> References: <1324551168-1202-1-git-send-email-chander.kashyap@linaro.org> Cc: linaro-dev@lists.linaro.org, bjlee@samsung.com, patches@linaro.org, mk7.kang@samsung.com, samsung@lists.linaro.org Subject: [U-Boot] [PATCH 3/6] Exynos: Clock.c: Replace exynos4 prefix with exynos X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Replace exynos4 prefix with exynos in arch/arm/cpu/armv7/exynos/clock.c as clock.c is common for exynos architecture. By doing so automatic selection of appropriate clock structure can be done. As per above reason replace exynos4_clock to exynos_clock in clock.h header file. Signed-off-by: Chander Kashyap --- arch/arm/cpu/armv7/exynos/clock.c | 50 +++++++++++++++--------------- arch/arm/include/asm/arch-exynos/clock.h | 2 +- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4d92c53..b101f96 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,11 +26,11 @@ #include #include -/* exynos4: return pll clock frequency */ -static unsigned long exynos4_get_pll_clk(int pllreg) +/* exynos: return pll clock frequency */ +static unsigned long exynos_get_pll_clk(int pllreg) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); + struct exynos_clock *clk = + (struct exynos_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; unsigned int freq; @@ -92,11 +92,11 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; } -/* exynos4: return ARM clock frequency */ -static unsigned long exynos4_get_arm_clk(void) +/* exynos: return ARM clock frequency */ +static unsigned long exynos_get_arm_clk(void) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); + struct exynos_clock *clk = + (struct exynos_clock *)samsung_get_base_clock(); unsigned long div; unsigned long armclk; unsigned int core_ratio; @@ -114,11 +114,11 @@ static unsigned long exynos4_get_arm_clk(void) return armclk; } -/* exynos4: return pwm clock frequency */ -static unsigned long exynos4_get_pwm_clk(void) +/* exynos: return pwm clock frequency */ +static unsigned long exynos_get_pwm_clk(void) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); + struct exynos_clock *clk = + (struct exynos_clock *)samsung_get_base_clock(); unsigned long pclk, sclk; unsigned int sel; unsigned int ratio; @@ -157,11 +157,11 @@ static unsigned long exynos4_get_pwm_clk(void) return pclk; } -/* exynos4: return uart clock frequency */ -static unsigned long exynos4_get_uart_clk(int dev_index) +/* exynos: return uart clock frequency */ +static unsigned long exynos_get_uart_clk(int dev_index) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); + struct exynos_clock *clk = + (struct exynos_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel; unsigned int ratio; @@ -204,11 +204,11 @@ static unsigned long exynos4_get_uart_clk(int dev_index) return uclk; } -/* exynos4: set the mmc clock */ -static void exynos4_set_mmc_clk(int dev_index, unsigned int div) +/* exynos: set the mmc clock */ +static void exynos_set_mmc_clk(int dev_index, unsigned int div) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); + struct exynos_clock *clk = + (struct exynos_clock *)samsung_get_base_clock(); unsigned int addr; unsigned int val; @@ -233,25 +233,25 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) unsigned long get_pll_clk(int pllreg) { - return exynos4_get_pll_clk(pllreg); + return exynos_get_pll_clk(pllreg); } unsigned long get_arm_clk(void) { - return exynos4_get_arm_clk(); + return exynos_get_arm_clk(); } unsigned long get_pwm_clk(void) { - return exynos4_get_pwm_clk(); + return exynos_get_pwm_clk(); } unsigned long get_uart_clk(int dev_index) { - return exynos4_get_uart_clk(dev_index); + return exynos_get_uart_clk(dev_index); } void set_mmc_clk(int dev_index, unsigned int div) { - exynos4_set_mmc_clk(dev_index, div); + exynos_set_mmc_clk(dev_index, div); } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 483c911..ecd0cb1 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -23,7 +23,7 @@ #define __ASM_ARM_ARCH_CLOCK_H_ #ifndef __ASSEMBLY__ -struct exynos4_clock { +struct exynos_clock { unsigned char res1[0x4200]; unsigned int src_leftbus; unsigned char res2[0x1fc];