From patchwork Thu Dec 22 10:52:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 132810 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5673AB714B for ; Thu, 22 Dec 2011 21:53:48 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E57828138; Thu, 22 Dec 2011 11:53:45 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T2f1VJWSAqGi; Thu, 22 Dec 2011 11:53:45 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A34E928142; Thu, 22 Dec 2011 11:53:37 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AD4A12813B for ; Thu, 22 Dec 2011 11:53:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QEqYj-XdY2gg for ; Thu, 22 Dec 2011 11:53:33 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-iy0-f172.google.com (mail-iy0-f172.google.com [209.85.210.172]) by theia.denx.de (Postfix) with ESMTPS id 20737280E4 for ; Thu, 22 Dec 2011 11:53:25 +0100 (CET) Received: by mail-iy0-f172.google.com with SMTP id n33so4773517iae.3 for ; Thu, 22 Dec 2011 02:53:25 -0800 (PST) Received: by 10.50.170.35 with SMTP id aj3mr8293924igc.2.1324551205316; Thu, 22 Dec 2011 02:53:25 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id f32sm24601659ibf.9.2011.12.22.02.53.21 (version=SSLv3 cipher=OTHER); Thu, 22 Dec 2011 02:53:24 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Date: Thu, 22 Dec 2011 16:22:44 +0530 Message-Id: <1324551168-1202-3-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1324551168-1202-1-git-send-email-chander.kashyap@linaro.org> References: <1324551168-1202-1-git-send-email-chander.kashyap@linaro.org> Cc: linaro-dev@lists.linaro.org, bjlee@samsung.com, patches@linaro.org, mk7.kang@samsung.com, samsung@lists.linaro.org Subject: [U-Boot] [PATCH 2/6] Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (EXYNOS4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap --- arch/arm/cpu/armv7/exynos/clock.c | 6 +----- include/configs/s5pc210_universal.h | 1 + 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 0c199cd..4d92c53 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,10 +26,6 @@ #include #include -#ifndef CONFIG_SYS_CLK_FREQ_C210 -#define CONFIG_SYS_CLK_FREQ_C210 24000000 -#endif - /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg) /* SDIV [2:0] */ s = r & 0x7; - freq = CONFIG_SYS_CLK_FREQ_C210; + freq = CONFIG_SYS_CLK_FREQ; if (pllreg == EPLL) { k = k & 0xffff; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 33c4600..18de956 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -50,6 +50,7 @@ /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */ #define CONFIG_SYS_CLK_FREQ_C210 24000000 +#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG