From patchwork Sun Nov 6 11:54:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Graeme Russ X-Patchwork-Id: 123919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4E1331007D3 for ; Sun, 6 Nov 2011 22:55:36 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A50C128EAA; Sun, 6 Nov 2011 12:55:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K2PMippFrQR6; Sun, 6 Nov 2011 12:55:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1A30528E97; Sun, 6 Nov 2011 12:55:08 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BDDB728C18 for ; Sun, 6 Nov 2011 12:55:03 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hyymeagCLyD1 for ; Sun, 6 Nov 2011 12:55:03 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-iy0-f172.google.com (mail-iy0-f172.google.com [209.85.210.172]) by theia.denx.de (Postfix) with ESMTPS id 07C5328AB5 for ; Sun, 6 Nov 2011 12:55:02 +0100 (CET) Received: by iaeo4 with SMTP id o4so4712729iae.3 for ; Sun, 06 Nov 2011 03:55:01 -0800 (PST) Received: by 10.231.9.40 with SMTP id j40mr2159913ibj.59.1320580501570; Sun, 06 Nov 2011 03:55:01 -0800 (PST) Received: from localhost.localdomain (d122-104-32-210.sbr6.nsw.optusnet.com.au. [122.104.32.210]) by mx.google.com with ESMTPS id 4sm26975559pbj.18.2011.11.06.03.54.59 (version=SSLv3 cipher=OTHER); Sun, 06 Nov 2011 03:55:01 -0800 (PST) From: Graeme Russ To: u-boot@lists.denx.de Date: Sun, 6 Nov 2011 22:54:47 +1100 Message-Id: <1320580490-8495-3-git-send-email-graeme.russ@gmail.com> X-Mailer: git-send-email 1.7.5.2.317.g391b14 In-Reply-To: <1320580490-8495-1-git-send-email-graeme.russ@gmail.com> References: <1320580490-8495-1-git-send-email-graeme.russ@gmail.com> Cc: Graeme Russ Subject: [U-Boot] [PATCH 2/5] cosmetic: checkpatch cleanup arch/x86/cpu/*.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Graeme Russ --- ./checkpatch.pl --no-tree -f arch/x86/cpu/*.c total: 0 errors, 0 warnings, 157 lines checked arch/x86/cpu/cpu.c has no obvious style problems and is ready for submission. total: 0 errors, 0 warnings, 675 lines checked arch/x86/cpu/interrupts.c has no obvious style problems and is ready for submission. arch/x86/cpu/cpu.c | 22 +++++++++++----------- arch/x86/cpu/interrupts.c | 29 +++++++++++++++-------------- 2 files changed, 26 insertions(+), 25 deletions(-) -- 1.7.5.2.317.g391b14 diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index cac12c0..48d2f7a 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -52,7 +52,7 @@ struct gdt_ptr { u16 len; u32 ptr; -} __attribute__((packed)); +} __packed; static void reload_gdt(void) { @@ -115,14 +115,14 @@ int x86_cpu_init_r(void) reload_gdt(); /* Initialize core interrupt and exception functionality of CPU */ - cpu_init_interrupts (); + cpu_init_interrupts(); return 0; } int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - printf ("resetting ...\n"); + printf("resetting ...\n"); /* wait 50 ms */ udelay(50000); @@ -133,7 +133,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -void flush_cache (unsigned long dummy1, unsigned long dummy2) +void flush_cache(unsigned long dummy1, unsigned long dummy2) { asm("wbinvd\n"); } @@ -142,16 +142,16 @@ void __attribute__ ((regparm(0))) generate_gpf(void); /* segment 0x70 is an arbitrary segment which does not exist */ asm(".globl generate_gpf\n" - ".hidden generate_gpf\n" - ".type generate_gpf, @function\n" - "generate_gpf:\n" - "ljmp $0x70, $0x47114711\n"); + ".hidden generate_gpf\n" + ".type generate_gpf, @function\n" + "generate_gpf:\n" + "ljmp $0x70, $0x47114711\n"); void __reset_cpu(ulong addr) { printf("Resetting using x86 Triple Fault\n"); - set_vector(13, generate_gpf); /* general protection fault handler */ - set_vector(8, generate_gpf); /* double fault handler */ - generate_gpf(); /* start the show */ + set_vector(13, generate_gpf); /* general protection fault handler */ + set_vector(8, generate_gpf); /* double fault handler */ + generate_gpf(); /* start the show */ } void reset_cpu(ulong addr) __attribute__((weak, alias("__reset_cpu"))); diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 89f39d2..07e945c 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -83,22 +83,22 @@ static inline unsigned long get_debugreg(int regno) switch (regno) { case 0: - asm("mov %%db0, %0" :"=r" (val)); + asm("mov %%db0, %0" : "=r" (val)); break; case 1: - asm("mov %%db1, %0" :"=r" (val)); + asm("mov %%db1, %0" : "=r" (val)); break; case 2: - asm("mov %%db2, %0" :"=r" (val)); + asm("mov %%db2, %0" : "=r" (val)); break; case 3: - asm("mov %%db3, %0" :"=r" (val)); + asm("mov %%db3, %0" : "=r" (val)); break; case 6: - asm("mov %%db6, %0" :"=r" (val)); + asm("mov %%db6, %0" : "=r" (val)); break; case 7: - asm("mov %%db7, %0" :"=r" (val)); + asm("mov %%db7, %0" : "=r" (val)); break; default: val = 0; @@ -120,7 +120,8 @@ void dump_regs(struct irq_regs *regs) printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n", regs->esi, regs->edi, regs->ebp, regs->esp); printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n", - (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss); + (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, + (u16)regs->xgs, (u16)regs->xss); cr0 = read_cr0(); cr2 = read_cr2(); @@ -164,13 +165,13 @@ struct idt_entry { u8 res; u8 access; u16 base_high; -} __attribute__ ((packed)); +} __packed; struct desc_ptr { unsigned short size; unsigned long address; unsigned short segment; -} __attribute__((packed)); +} __packed; struct idt_entry idt[256]; @@ -178,7 +179,7 @@ struct desc_ptr idt_ptr; static inline void load_idt(const struct desc_ptr *dtr) { - asm volatile("cs lidt %0"::"m" (*dtr)); + asm volatile("cs lidt %0" : : "m" (*dtr)); } void set_vector(u8 intnum, void *routine) @@ -187,8 +188,8 @@ void set_vector(u8 intnum, void *routine) idt[intnum].base_low = (u16)((u32)(routine) & 0xffff); } -void irq_0(void); -void irq_1(void); +static void irq_0(void); +static void irq_1(void); int cpu_init_interrupts(void) { @@ -201,7 +202,7 @@ int cpu_init_interrupts(void) disable_interrupts(); /* Setup the IDT */ - for (i=0;i<256;i++) { + for (i = 0; i < 256; i++) { idt[i].access = 0x8e; idt[i].res = 0; idt[i].selector = 0x10; @@ -238,7 +239,7 @@ int disable_interrupts(void) asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : ); - return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */ + return flags & X86_EFLAGS_IF; } /* IRQ Low-Level Service Routine */