From patchwork Thu Oct 20 19:03:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 120854 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 41DCA1007D1 for ; Fri, 21 Oct 2011 06:04:56 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 00AB028AC3; Thu, 20 Oct 2011 21:04:55 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KAQr+aIkZAZy; Thu, 20 Oct 2011 21:04:54 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 57F9828F65; Thu, 20 Oct 2011 21:04:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1E742908B for ; Thu, 20 Oct 2011 21:04:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qMZ4v5FP8qxj for ; Thu, 20 Oct 2011 21:04:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp-out.google.com (smtp-out.google.com [216.239.44.51]) by theia.denx.de (Postfix) with ESMTPS id 151DF290E2 for ; Thu, 20 Oct 2011 21:04:44 +0200 (CEST) Received: from hpaq1.eem.corp.google.com (hpaq1.eem.corp.google.com [172.25.149.1]) by smtp-out.google.com with ESMTP id p9KJ4TGh030714; Thu, 20 Oct 2011 12:04:29 -0700 Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by hpaq1.eem.corp.google.com with ESMTP id p9KJ4RxF000650; Thu, 20 Oct 2011 12:04:28 -0700 Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id 37380140D94; Thu, 20 Oct 2011 12:04:27 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Thu, 20 Oct 2011 12:03:22 -0700 Message-Id: <1319137409-4132-2-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.3.1 In-Reply-To: <1319137409-4132-1-git-send-email-sjg@chromium.org> References: <1319137409-4132-1-git-send-email-sjg@chromium.org> X-System-Of-Record: true Cc: Tom Warren Subject: [U-Boot] [PATCH 1/8] tegra2: Tidy UART selection X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de UART selection is done with a lot of #ifdefs. This cleans things up a little. Signed-off-by: Simon Glass --- board/nvidia/common/board.c | 57 +++++++++++++++++++++++++----------------- 1 files changed, 34 insertions(+), 23 deletions(-) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 0f12de2..a5da310 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -35,6 +35,12 @@ DECLARE_GLOBAL_DATA_PTR; +enum { + /* UARTs which we can enable */ + UARTA = 1 << 0, + UARTD = 1 << 3, +}; + const struct tegra2_sysinfo sysinfo = { CONFIG_TEGRA2_BOARD_STRING }; @@ -64,36 +70,32 @@ static void enable_uart(enum periph_id pid) /* * Routine: clock_init_uart - * Description: init the PLL and clock for the UART(s) + * Description: init clock for the UART(s) */ -static void clock_init_uart(void) +static void clock_init_uart(int uart_ids) { -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - enable_uart(PERIPH_ID_UART1); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - enable_uart(PERIPH_ID_UART4); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ + if (uart_ids & UARTA) + enable_uart(PERIPH_ID_UART1); + if (uart_ids & UARTD) + enable_uart(PERIPH_ID_UART4); } /* * Routine: pin_mux_uart * Description: setup the pin muxes/tristate values for the UART(s) */ -static void pin_mux_uart(void) +static void pin_mux_uart(int uart_ids) { -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); - - pinmux_tristate_disable(PINGRP_IRRX); - pinmux_tristate_disable(PINGRP_IRTX); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); - - pinmux_tristate_disable(PINGRP_GMC); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ + if (uart_ids & UARTA) { + pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_IRRX); + pinmux_tristate_disable(PINGRP_IRTX); + } + if (uart_ids & UARTD) { + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); + pinmux_tristate_disable(PINGRP_GMC); + } } /* @@ -114,14 +116,23 @@ int board_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { + int uart_ids = 0; /* bit mask of which UART ids to enable */ + +#ifdef CONFIG_TEGRA2_ENABLE_UARTA + uart_ids |= UARTA; +#endif +#ifdef CONFIG_TEGRA2_ENABLE_UARTD + uart_ids |= UARTD; +#endif + /* Initialize essential common plls */ clock_early_init(); /* Initialize UART clocks */ - clock_init_uart(); + clock_init_uart(uart_ids); /* Initialize periph pinmuxes */ - pin_mux_uart(); + pin_mux_uart(uart_ids); /* Initialize periph GPIOs */ gpio_config_uart();