From patchwork Wed Aug 24 16:40:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 111383 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 145F9B6F18 for ; Thu, 25 Aug 2011 02:40:53 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2402528091; Wed, 24 Aug 2011 18:40:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VCeCAj2eDEmo; Wed, 24 Aug 2011 18:40:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B920728094; Wed, 24 Aug 2011 18:40:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 998F428088 for ; Wed, 24 Aug 2011 18:40:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Rb1cmGMqfj95 for ; Wed, 24 Aug 2011 18:40:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1ehsobe003.messaging.microsoft.com [216.32.181.183]) by theia.denx.de (Postfix) with ESMTPS id 3012D2807B for ; Wed, 24 Aug 2011 18:40:37 +0200 (CEST) Received: from mail83-ch1-R.bigfish.com (216.32.181.170) by CH1EHSOBE004.bigfish.com (10.43.70.54) with Microsoft SMTP Server id 14.1.225.22; Wed, 24 Aug 2011 16:40:36 +0000 Received: from mail83-ch1 (localhost.localdomain [127.0.0.1]) by mail83-ch1-R.bigfish.com (Postfix) with ESMTP id 5A94D1458072 for ; Wed, 24 Aug 2011 16:40:36 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zz853kzz1202hzz8275bhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail83-ch1 (localhost.localdomain [127.0.0.1]) by mail83-ch1 (MessageSwitch) id 1314204036146910_18892; Wed, 24 Aug 2011 16:40:36 +0000 (UTC) Received: from CH1EHSMHS035.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.252]) by mail83-ch1.bigfish.com (Postfix) with ESMTP id 1F5AF189804F for ; Wed, 24 Aug 2011 16:40:36 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS035.bigfish.com (10.43.70.35) with Microsoft SMTP Server (TLS) id 14.1.225.22; Wed, 24 Aug 2011 16:40:34 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.323.2; Wed, 24 Aug 2011 11:40:31 -0500 Received: from localhost.localdomain ([10.214.84.166]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7OGeSua004878; Wed, 24 Aug 2011 11:40:30 -0500 (CDT) From: York Sun To: Date: Wed, 24 Aug 2011 09:40:27 -0700 Message-ID: <1314204027-9982-3-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1314204027-9982-1-git-send-email-yorksun@freescale.com> References: <1314204027-9982-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH 3/3] powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de RDIMM has different timing parameters from UDIMM. Create new tables for RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for future use. Signed-off-by: York Sun --- board/freescale/corenet_ds/ddr.c | 103 +++++++++++++++++++++++++++++++------- 1 files changed, 84 insertions(+), 19 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index e3b3855..10ff4e7 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -118,53 +118,111 @@ typedef struct { u32 force_2T; } board_specific_parameters_t; -/* ranges for parameters: - * wr_data_delay = 0-6 - * clk adjust = 0-8 - * cpo 2-0x1E (30) - */ - - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][30] = { +const board_specific_parameters_t board_specific_parameters_udimm[][30] = { { /* * memory controller 0 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * mhz| mhz|ranks|adjst| start | |delay | */ { 0, 850, 4, 4, 6, 0xff, 2, 0}, {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, { 0, 850, 2, 5, 6, 0xff, 2, 0}, {851, 950, 2, 5, 7, 0xff, 2, 0}, {951, 1050, 2, 5, 7, 0xff, 2, 0}, {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + {1351, 1666, 2, 5, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, }, { /* * memory controller 1 * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * mhz| mhz|ranks|adjst| start | |delay | */ { 0, 850, 4, 4, 6, 0xff, 2, 0}, {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, { 0, 850, 2, 5, 6, 0xff, 2, 0}, {851, 950, 2, 5, 7, 0xff, 2, 0}, {951, 1050, 2, 5, 7, 0xff, 2, 0}, {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, + {1351, 1666, 2, 5, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, + } +}; + +const board_specific_parameters_t board_specific_parameters_rdimm[][30] = { + { + /* + * memory controller 0 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | |delay | + */ + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, + { 0, 850, 2, 4, 6, 0xff, 2, 0}, + {851, 950, 2, 4, 7, 0xff, 2, 0}, + {951, 1050, 2, 4, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 8, 0xff, 2, 0}, + {1251, 1350, 2, 4, 8, 0xff, 2, 0}, + {1351, 1666, 2, 4, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, + }, + + { + /* + * memory controller 1 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | |delay | + */ + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + {1351, 1666, 4, 5, 12, 0xff, 2, 0}, + { 0, 850, 2, 4, 6, 0xff, 2, 0}, + {851, 950, 2, 4, 7, 0xff, 2, 0}, + {951, 1050, 2, 4, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 8, 0xff, 2, 0}, + {1251, 1350, 2, 4, 8, 0xff, 2, 0}, + {1351, 1666, 2, 4, 8, 0xff, 2, 0}, + { 0, 850, 1, 4, 5, 0xff, 2, 0}, + {851, 950, 1, 4, 7, 0xff, 2, 0}, + {951, 1050, 1, 4, 8, 0xff, 2, 0}, + {1051, 1250, 1, 4, 8, 0xff, 2, 0}, + {1251, 1350, 1, 4, 8, 0xff, 2, 0}, + {1351, 1666, 1, 4, 8, 0xff, 2, 0}, } }; @@ -172,13 +230,20 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp = - &(board_specific_parameters[ctrl_num][0]); - u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / - sizeof(board_specific_parameters[0][0]); + const board_specific_parameters_t *pbsp; + u32 num_params; u32 i; ulong ddr_freq; + if (popts->registered_dimm_en) { + pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]); + num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) / + sizeof(board_specific_parameters_rdimm[0][0]); + } else { + pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); + num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / + sizeof(board_specific_parameters_udimm[0][0]); + } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */