From patchwork Wed Aug 17 14:14:09 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: nagabhushana.netagunte@ti.com X-Patchwork-Id: 110323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BEAAFB6F9D for ; Thu, 18 Aug 2011 00:15:36 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 74516280C4; Wed, 17 Aug 2011 16:15:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Cmrp59hZ51jG; Wed, 17 Aug 2011 16:15:11 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F87B28088; Wed, 17 Aug 2011 16:14:38 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 127F72807F for ; Wed, 17 Aug 2011 16:14:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lLrEP18HD4I4 for ; Wed, 17 Aug 2011 16:14:29 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 9C2CC28084 for ; Wed, 17 Aug 2011 16:14:22 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7HEEIeh001521 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 17 Aug 2011 09:14:20 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7HEEHKp014999 for ; Wed, 17 Aug 2011 19:44:17 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Wed, 17 Aug 2011 19:44:17 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7HEEFV1006149; Wed, 17 Aug 2011 19:44:16 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p7HEEFKI000320; Wed, 17 Aug 2011 19:44:15 +0530 Received: (from x0144960@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p7HEEFJZ000317; Wed, 17 Aug 2011 19:44:15 +0530 From: To: Date: Wed, 17 Aug 2011 19:44:09 +0530 Message-ID: <1313590455-32737-3-git-send-email-nagabhushana.netagunte@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1313590455-32737-1-git-send-email-nagabhushana.netagunte@ti.com> References: <1313590455-32737-1-git-send-email-nagabhushana.netagunte@ti.com> MIME-Version: 1.0 Cc: Nagabhushana Netagunte , sudhakar.raj@ti.com, manjunath.hadli@ti.com Subject: [U-Boot] [PATCH v3 2/8] da8xx: add support for multiple PLL controllers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Sudhakar Rajashekhara Modify clk_get() function in cpu file to work for multiple PLL controllers. Signed-off-by: Sudhakar Rajashekhara Signed-off-by: Nagabhushana Netagunte --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 30 ++++++++++++++++--------- arch/arm/include/asm/arch-davinci/hardware.h | 4 ++- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 8b57205..b705dfd 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -37,6 +37,7 @@ #define PLLC_PLLDIV4 0x160 #define PLLC_PLLDIV5 0x164 #define PLLC_PLLDIV6 0x168 +#define PLLC_PLLDIV7 0x16c #define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV9 0x174 @@ -61,11 +62,9 @@ #endif #ifdef CONFIG_SOC_DA8XX -const dv_reg * const sysdiv[7] = { - &davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2, - &davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4, - &davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6, - &davinci_pllc_regs->plldiv7 +unsigned int sysdiv[9] = { + PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, + PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 }; int clk_get(enum davinci_clk_ids id) @@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id) int pllm; int post_div; int pll_out; + unsigned int pll_base; pll_out = CONFIG_SYS_OSCIN_FREQ; if (id == DAVINCI_AUXCLK_CLKID) goto out; + if ((id >> 16) == 1) + pll_base = (unsigned int)davinci_pllc1_regs; + else + pll_base = (unsigned int)davinci_pllc0_regs; + + id &= 0xFFFF; + /* * Lets keep this simple. Combining operations can result in * unexpected approximations */ - pre_div = (readl(&davinci_pllc_regs->prediv) & - DAVINCI_PLLC_DIV_MASK) + 1; - pllm = readl(&davinci_pllc_regs->pllm) + 1; + pre_div = (readl(pll_base + PLLC_PREDIV) & + DAVINCI_PLLC_DIV_MASK) + 1; + pllm = readl(pll_base + PLLC_PLLM) + 1; pll_out /= pre_div; pll_out *= pllm; @@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id) if (id == DAVINCI_PLLM_CLKID) goto out; - post_div = (readl(&davinci_pllc_regs->postdiv) & - DAVINCI_PLLC_DIV_MASK) + 1; + post_div = (readl(pll_base + PLLC_POSTDIV) & + DAVINCI_PLLC_DIV_MASK) + 1; pll_out /= post_div; if (id == DAVINCI_PLLC_CLKID) goto out; - pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1; + pll_out /= (readl(pll_base + sysdiv[id - 1]) & + DAVINCI_PLLC_DIV_MASK) + 1; out: return pll_out; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index f537c4b..646e2ce 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_TIMER1_BASE 0x01c21000 #define DAVINCI_WDOG_BASE 0x01c21000 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 +#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000 #define DAVINCI_PSC0_BASE 0x01c10000 #define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_SPI0_BASE 0x01c41000 @@ -387,7 +388,8 @@ struct davinci_pllc_regs { dv_reg emucnt1; }; -#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) +#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f #define ASYNC3 get_async3_src()