| Message ID | 1312197486-31712-2-git-send-email-aneesh@ti.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
Hi Albert, On Monday 01 August 2011 04:48 PM, Aneesh V wrote: > c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable() > to board_init_r(). This enables d-cache for all ARM boards. > As a result some of the arm boards that are not cache-ready > are broken. Revert this change and allow platform code to > take the decision on d-cache enabling. > > Also add some documentation for cache usage in ARM. > > Signed-off-by: Aneesh V<aneesh@ti.com> > --- > MAKEALL pending. Will update the results tomorrow. > --- > arch/arm/lib/board.c | 8 +++----- > arch/arm/lib/cache.c | 12 ++++++++++++ > doc/README.arm-caches | 40 ++++++++++++++++++++++++++++++++++++++++ > include/common.h | 1 + > 4 files changed, 56 insertions(+), 5 deletions(-) > create mode 100644 doc/README.arm-caches > > diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c > index 90709d0..d093d5b 100644 > --- a/arch/arm/lib/board.c > +++ b/arch/arm/lib/board.c > @@ -446,11 +446,9 @@ void board_init_r (gd_t *id, ulong dest_addr) > gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ > > monitor_flash_len = _end_ofs; > - /* > - * Enable D$: > - * I$, if needed, must be already enabled in start.S > - */ > - dcache_enable(); > + > + /* Enable caches */ > + enable_caches(); > > debug ("monitor flash len: %08lX\n", monitor_flash_len); > board_init(); /* Setup chipselects */ > diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c > index 92b61a2..b545fb7 100644 > --- a/arch/arm/lib/cache.c > +++ b/arch/arm/lib/cache.c > @@ -53,3 +53,15 @@ void __flush_dcache_all(void) > } > void flush_dcache_all(void) > __attribute__((weak, alias("__flush_dcache_all"))); > + > + > +/* > + * Default implementation of enable_caches() > + * Real implementation should be in platform code > + */ > +void __enable_caches(void) > +{ > + puts("WARNING: Caches not enabled\n"); > +} > +void enable_caches(void) > + __attribute__((weak, alias("__enable_caches"))); > diff --git a/doc/README.arm-caches b/doc/README.arm-caches > new file mode 100644 > index 0000000..9edc252 > --- /dev/null > +++ b/doc/README.arm-caches > @@ -0,0 +1,40 @@ > +Disabling I-cache: > +- Set CONFIG_SYS_ICACHE_OFF > + > +Disabling D-cache: > +- Set CONFIG_SYS_DCACHE_OFF > + > +Enabling I-cache: > +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable(). > + > +Enabling D-cache: > +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call dcache_enable(). > + > +Enabling Caches at System Startup: > +- Implement enable_caches() for your platform and enable the I-cache and > + D-cache from this function. This function is called immediately > + after relocation. > + > +Guidelines for Working with D-cache: > + > +Memory to Peripheral DMA: > +- Flush the buffer after the MPU writes the data and before the DMA is > + initiated. > + > +Peripheral to Memory DMA: > +- Invalidate the buffer after the DMA is complete and before the MPU reads > + it. The other discussion we are having about caches made me realize that I need to improve the above guideline like this: Peripheral to Memory DMA: - Invalidate the buffer before starting the DMA(This is for preventing cache-line replacements from corrupting the DMA buffer during the course of DMA). - Invalidate the buffer after the DMA is complete and before the MPU reads it. I shall submit an updated patch for this. best regards, Aneesh
Hi Aneesh, Le 05/08/2011 17:07, Aneesh V a écrit : > Hi Albert, > > On Monday 01 August 2011 04:48 PM, Aneesh V wrote: >> c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable() >> to board_init_r(). This enables d-cache for all ARM boards. >> As a result some of the arm boards that are not cache-ready >> are broken. Revert this change and allow platform code to >> take the decision on d-cache enabling. >> >> Also add some documentation for cache usage in ARM. >> >> Signed-off-by: Aneesh V<aneesh@ti.com> >> --- >> MAKEALL pending. Will update the results tomorrow. >> --- >> arch/arm/lib/board.c | 8 +++----- >> arch/arm/lib/cache.c | 12 ++++++++++++ >> doc/README.arm-caches | 40 ++++++++++++++++++++++++++++++++++++++++ >> include/common.h | 1 + >> 4 files changed, 56 insertions(+), 5 deletions(-) >> create mode 100644 doc/README.arm-caches >> >> diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c >> index 90709d0..d093d5b 100644 >> --- a/arch/arm/lib/board.c >> +++ b/arch/arm/lib/board.c >> @@ -446,11 +446,9 @@ void board_init_r (gd_t *id, ulong dest_addr) >> gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ >> >> monitor_flash_len = _end_ofs; >> - /* >> - * Enable D$: >> - * I$, if needed, must be already enabled in start.S >> - */ >> - dcache_enable(); >> + >> + /* Enable caches */ >> + enable_caches(); >> >> debug ("monitor flash len: %08lX\n", monitor_flash_len); >> board_init(); /* Setup chipselects */ >> diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c >> index 92b61a2..b545fb7 100644 >> --- a/arch/arm/lib/cache.c >> +++ b/arch/arm/lib/cache.c >> @@ -53,3 +53,15 @@ void __flush_dcache_all(void) >> } >> void flush_dcache_all(void) >> __attribute__((weak, alias("__flush_dcache_all"))); >> + >> + >> +/* >> + * Default implementation of enable_caches() >> + * Real implementation should be in platform code >> + */ >> +void __enable_caches(void) >> +{ >> + puts("WARNING: Caches not enabled\n"); >> +} >> +void enable_caches(void) >> + __attribute__((weak, alias("__enable_caches"))); >> diff --git a/doc/README.arm-caches b/doc/README.arm-caches >> new file mode 100644 >> index 0000000..9edc252 >> --- /dev/null >> +++ b/doc/README.arm-caches >> @@ -0,0 +1,40 @@ >> +Disabling I-cache: >> +- Set CONFIG_SYS_ICACHE_OFF >> + >> +Disabling D-cache: >> +- Set CONFIG_SYS_DCACHE_OFF >> + >> +Enabling I-cache: >> +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable(). >> + >> +Enabling D-cache: >> +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call dcache_enable(). >> + >> +Enabling Caches at System Startup: >> +- Implement enable_caches() for your platform and enable the I-cache and >> + D-cache from this function. This function is called immediately >> + after relocation. >> + >> +Guidelines for Working with D-cache: >> + >> +Memory to Peripheral DMA: >> +- Flush the buffer after the MPU writes the data and before the DMA is >> + initiated. >> + >> +Peripheral to Memory DMA: >> +- Invalidate the buffer after the DMA is complete and before the MPU >> reads >> + it. > > The other discussion we are having about caches made me realize that I > need to improve the above guideline like this: > > Peripheral to Memory DMA: > - Invalidate the buffer before starting the DMA(This is for preventing > cache-line replacements from corrupting the DMA buffer during the > course of DMA). Correct, but maybe you should indicate why this happens (not all people will realize that some *other* use of the cache might cause eviction of a cache line, thus a possible unexpected flush). > - Invalidate the buffer after the DMA is complete and before the MPU > reads it. > > I shall submit an updated patch for this. Thanks! > best regards, > Aneesh Amicalement,
- Avoid enabling caches for all ARM boards - Enable caches for omap3/4 - Stronger barrier for armv7 cache-maintenance operations. V2: * Rebased to latest HEAD of u-boot/master * Improved the README * Added a patch for removing the flush in invalidate and for printing a warning in such cases. Aneesh V (4): arm: do not force d-cache enable on all boards omap: enable caches at system start-up armv7: stronger barrier for cache-maintenance operations armv7: cache: remove flush on un-aligned invalidate arch/arm/cpu/armv7/cache_v7.c | 26 ++++++++++--------- arch/arm/cpu/armv7/omap3/board.c | 8 ++++++ arch/arm/cpu/armv7/omap4/board.c | 8 ++++++ arch/arm/lib/board.c | 8 ++--- arch/arm/lib/cache-pl310.c | 15 ++++++---- arch/arm/lib/cache.c | 12 +++++++++ doc/README.arm-caches | 51 ++++++++++++++++++++++++++++++++++++++ include/common.h | 1 + 8 files changed, 106 insertions(+), 23 deletions(-) create mode 100644 doc/README.arm-caches
Hi Wolfgang, Albert, On Tuesday 09 August 2011 04:40 PM, Aneesh V wrote: > - Avoid enabling caches for all ARM boards > - Enable caches for omap3/4 > - Stronger barrier for armv7 cache-maintenance operations. > > V2: > * Rebased to latest HEAD of u-boot/master > * Improved the README > * Added a patch for removing the flush in invalidate > and for printing a warning in such cases. I forgot to add v2 tag in the subject line for this series. Shall I reject and archive these patches in patchworks? best regards, Aneesh
- Avoid enabling caches for all ARM boards - Enable caches for omap3/4 - Stronger barrier for armv7 cache-maintenance operations. V2: * Rebased to latest HEAD of u-boot/master * Improved the README * Added a patch for removing the flush in invalidate and for printing a warning in such cases. Aneesh V (4): arm: do not force d-cache enable on all boards omap: enable caches at system start-up armv7: stronger barrier for cache-maintenance operations armv7: cache: remove flush on un-aligned invalidate arch/arm/cpu/armv7/cache_v7.c | 26 ++++++++++--------- arch/arm/cpu/armv7/omap3/board.c | 8 ++++++ arch/arm/cpu/armv7/omap4/board.c | 8 ++++++ arch/arm/lib/board.c | 8 ++--- arch/arm/lib/cache-pl310.c | 15 ++++++---- arch/arm/lib/cache.c | 12 +++++++++ doc/README.arm-caches | 51 ++++++++++++++++++++++++++++++++++++++ include/common.h | 1 + 8 files changed, 106 insertions(+), 23 deletions(-) create mode 100644 doc/README.arm-caches
- Avoid enabling caches for all ARM boards - Enable caches for omap3/4 - Stronger barrier for armv7 cache-maintenance operations. V2: * Rebased to latest HEAD of u-boot/master * Improved the README * Added a patch for removing the flush in invalidate and for printing a warning in such cases. V3: * Improve the error message on un-aligned invalidate Aneesh V (4): arm: do not force d-cache enable on all boards omap: enable caches at system start-up armv7: stronger barrier for cache-maintenance operations armv7: cache: remove flush on un-aligned invalidate arch/arm/cpu/armv7/cache_v7.c | 26 ++++++++++--------- arch/arm/cpu/armv7/omap3/board.c | 8 ++++++ arch/arm/cpu/armv7/omap4/board.c | 8 ++++++ arch/arm/lib/board.c | 8 ++--- arch/arm/lib/cache-pl310.c | 15 ++++++---- arch/arm/lib/cache.c | 12 +++++++++ doc/README.arm-caches | 51 ++++++++++++++++++++++++++++++++++++++ include/common.h | 1 + 8 files changed, 106 insertions(+), 23 deletions(-) create mode 100644 doc/README.arm-caches
Le 11/08/2011 16:35, Aneesh V a écrit : > - Avoid enabling caches for all ARM boards > - Enable caches for omap3/4 > - Stronger barrier for armv7 cache-maintenance operations. > > V2: > * Rebased to latest HEAD of u-boot/master > * Improved the README > * Added a patch for removing the flush in invalidate > and for printing a warning in such cases. > > V3: > * Improve the error message on un-aligned invalidate > > Aneesh V (4): > arm: do not force d-cache enable on all boards > omap: enable caches at system start-up > armv7: stronger barrier for cache-maintenance operations > armv7: cache: remove flush on un-aligned invalidate > > arch/arm/cpu/armv7/cache_v7.c | 26 ++++++++++--------- > arch/arm/cpu/armv7/omap3/board.c | 8 ++++++ > arch/arm/cpu/armv7/omap4/board.c | 8 ++++++ > arch/arm/lib/board.c | 8 ++--- > arch/arm/lib/cache-pl310.c | 15 ++++++---- > arch/arm/lib/cache.c | 12 +++++++++ > doc/README.arm-caches | 51 ++++++++++++++++++++++++++++++++++++++ > include/common.h | 1 + > 8 files changed, 106 insertions(+), 23 deletions(-) > create mode 100644 doc/README.arm-caches Please in the future leave history in individual patches (but you can keep int in cover letters as well). That is a burden, but it provides for better tracking on patchwork, where cover letters are not recorded, and individual patches are the only place where history can appear. Amicalement,
Hi Albert, On Sat, Aug 13, 2011 at 3:39 PM, Albert ARIBAUD <albert.u.boot@aribaud.net> wrote: > Le 11/08/2011 16:35, Aneesh V a écrit : >> >> - Avoid enabling caches for all ARM boards >> - Enable caches for omap3/4 >> - Stronger barrier for armv7 cache-maintenance operations. >> >> V2: >> * Rebased to latest HEAD of u-boot/master >> * Improved the README >> * Added a patch for removing the flush in invalidate >> and for printing a warning in such cases. >> >> V3: >> * Improve the error message on un-aligned invalidate >> >> Aneesh V (4): >> arm: do not force d-cache enable on all boards >> omap: enable caches at system start-up >> armv7: stronger barrier for cache-maintenance operations >> armv7: cache: remove flush on un-aligned invalidate >> >> arch/arm/cpu/armv7/cache_v7.c | 26 ++++++++++--------- >> arch/arm/cpu/armv7/omap3/board.c | 8 ++++++ >> arch/arm/cpu/armv7/omap4/board.c | 8 ++++++ >> arch/arm/lib/board.c | 8 ++--- >> arch/arm/lib/cache-pl310.c | 15 ++++++---- >> arch/arm/lib/cache.c | 12 +++++++++ >> doc/README.arm-caches | 51 >> ++++++++++++++++++++++++++++++++++++++ >> include/common.h | 1 + >> 8 files changed, 106 insertions(+), 23 deletions(-) >> create mode 100644 doc/README.arm-caches > > Please in the future leave history in individual patches (but you can keep > int in cover letters as well). That is a burden, but it provides for better > tracking on patchwork, where cover letters are not recorded, and individual > patches are the only place where history can appear. I add history in both cover letter and in individual patches. However, I change the history of a patch only if there's some update in that revision. That is, I do not add something like: Changes in V2: None Is that fine? best regards, Aneesh
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 90709d0..d093d5b 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -446,11 +446,9 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ monitor_flash_len = _end_ofs; - /* - * Enable D$: - * I$, if needed, must be already enabled in start.S - */ - dcache_enable(); + + /* Enable caches */ + enable_caches(); debug ("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..b545fb7 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,15 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + + +/* + * Default implementation of enable_caches() + * Real implementation should be in platform code + */ +void __enable_caches(void) +{ + puts("WARNING: Caches not enabled\n"); +} +void enable_caches(void) + __attribute__((weak, alias("__enable_caches"))); diff --git a/doc/README.arm-caches b/doc/README.arm-caches new file mode 100644 index 0000000..9edc252 --- /dev/null +++ b/doc/README.arm-caches @@ -0,0 +1,40 @@ +Disabling I-cache: +- Set CONFIG_SYS_ICACHE_OFF + +Disabling D-cache: +- Set CONFIG_SYS_DCACHE_OFF + +Enabling I-cache: +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call icache_enable(). + +Enabling D-cache: +- Make sure CONFIG_SYS_ICACHE_OFF is not set and call dcache_enable(). + +Enabling Caches at System Startup: +- Implement enable_caches() for your platform and enable the I-cache and + D-cache from this function. This function is called immediately + after relocation. + +Guidelines for Working with D-cache: + +Memory to Peripheral DMA: +- Flush the buffer after the MPU writes the data and before the DMA is + initiated. + +Peripheral to Memory DMA: +- Invalidate the buffer after the DMA is complete and before the MPU reads + it. + +Buffer Requirements: +- Any buffer that is invalidated(that is, typically the peripheral to + memory DMA buffer) should be aligned to cache-line boundary both at + at the beginning and at the end of the buffer. + +Cleanup Before Linux: +- cleanup_before_linux() should flush the D-cache, invalidate I-cache, and + disable MMU and caches. +- The following sequence is advisable while disabling d-cache: + 1. disable_dcache() - flushes and disables d-cache + 2. invalidate_dcache_all() - invalid any entry that came to the cache + in the short period after the cache was flushed but before the + cache got disabled. diff --git a/include/common.h b/include/common.h index b994e70..c83b358 100644 --- a/include/common.h +++ b/include/common.h @@ -613,6 +613,7 @@ ulong lcd_setmem (ulong); ulong video_setmem (ulong); /* arch/$(ARCH)/lib/cache.c */ +void enable_caches(void); void flush_cache (unsigned long, unsigned long); void flush_dcache_all(void); void flush_dcache_range(unsigned long start, unsigned long stop);
c2dd0d45540397704de9b13287417d21049d34c6 added dcache_enable() to board_init_r(). This enables d-cache for all ARM boards. As a result some of the arm boards that are not cache-ready are broken. Revert this change and allow platform code to take the decision on d-cache enabling. Also add some documentation for cache usage in ARM. Signed-off-by: Aneesh V <aneesh@ti.com> --- MAKEALL pending. Will update the results tomorrow. --- arch/arm/lib/board.c | 8 +++----- arch/arm/lib/cache.c | 12 ++++++++++++ doc/README.arm-caches | 40 ++++++++++++++++++++++++++++++++++++++++ include/common.h | 1 + 4 files changed, 56 insertions(+), 5 deletions(-) create mode 100644 doc/README.arm-caches