From patchwork Tue Jun 28 14:14:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Schwarz X-Patchwork-Id: 102395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 27813B6F5D for ; Wed, 29 Jun 2011 00:23:40 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9449D2810A; Tue, 28 Jun 2011 16:23:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vR0XiCHhvCfV; Tue, 28 Jun 2011 16:23:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF0E3280FF; Tue, 28 Jun 2011 16:23:36 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 075F9280FF for ; Tue, 28 Jun 2011 16:23:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z6ONXqpaepn4 for ; Tue, 28 Jun 2011 16:23:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-fx0-f50.google.com (mail-fx0-f50.google.com [209.85.161.50]) by theia.denx.de (Postfix) with ESMTPS id 21D18280F6 for ; Tue, 28 Jun 2011 16:23:32 +0200 (CEST) Received: by fxh2 with SMTP id 2so198329fxh.23 for ; Tue, 28 Jun 2011 07:23:32 -0700 (PDT) Received: by 10.223.7.150 with SMTP id d22mr1529534fad.17.1309270530425; Tue, 28 Jun 2011 07:15:30 -0700 (PDT) Received: from localhost.localdomain (DSL01.212.114.252.242.ip-pool.NEFkom.net [212.114.252.242]) by mx.google.com with ESMTPS id r10sm166445fah.2.2011.06.28.07.15.28 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 28 Jun 2011 07:15:29 -0700 (PDT) From: simonschwarzcor@googlemail.com To: u-boot@lists.denx.de Date: Tue, 28 Jun 2011 16:14:39 +0200 Message-Id: <1309270480-31918-5-git-send-email-schwarz@corscience.de> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1309270480-31918-1-git-send-email-schwarz@corscience.de> References: <1309270480-31918-1-git-send-email-schwarz@corscience.de> Cc: Simon Schwarz Subject: [U-Boot] [4/5]devkit8000 nand_spl: Add SPL NAND support to omap_gpmc driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add support for NAND_SPL to omap gpmc driver. This means adding nand_read_buf16 to read from GPMC 32bit buffer (16 here means 16bit bus!) and adding omap_dev_ready as indicator if the GPMC is ready. Signed-off-by: Simon Schwarz diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 99b9cef..7dfb05d 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -29,6 +29,9 @@ #include #include + +#define GPMC_WAIT0_PIN_ACTIVE (1 << 8) + static uint8_t cs; static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT; @@ -61,6 +64,37 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, writeb(cmd, this->IO_ADDR_W); } +/* Check wait pin as dev ready indicator */ +int omap_dev_ready(struct mtd_info *mtd) +{ + return gpmc_cfg->status & GPMC_WAIT0_PIN_ACTIVE; +} + +#ifdef CONFIG_PRELOADER + +/** + * nand_read_buf16 - [DEFAULT] read chip data into buffer + * @mtd: MTD device structure + * @buf: buffer to store date + * @len: number of bytes to read + * + * Default read function for 16bit buswith + * + * This function is based on nand_read_buf16 from nand_base.c. This version + * reads 32bit not 16bit although the bus only has 16bit. + */ +static void gpmc_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + u32 *p = (u32 *) buf; + len >>= 2; + + for (i = 0; i < len; i++) + p[i] = readl(chip->IO_ADDR_R); +} +#endif + /* * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in * GPMC controller @@ -278,7 +312,9 @@ void omap_nand_switch_ecc(int32_t hardware) /* Update NAND handling after ECC mode switch */ nand_scan_tail(mtd); + #ifndef CONFIG_SPL nand->options &= ~NAND_OWN_BUFFERS; + #endif } /* @@ -337,8 +373,23 @@ int board_nand_init(struct nand_chip *nand) nand->options |= NAND_BUSWIDTH_16; nand->chip_delay = 100; + nand->dev_ready = omap_dev_ready; /* Default ECC mode */ +#ifndef CONFIG_PRELOADER nand->ecc.mode = NAND_ECC_SOFT; +#else + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 24; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + nand->read_buf = gpmc_read_buf16; + omap_hwecc_init(nand); +#endif return 0; } + +