diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index f723cfa..5b54e35 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -582,7 +582,7 @@ int fdt_get_node_and_value (void *blob,
 #if !defined(MACH_TYPE_KM_KIRKWOOD)
 int ethernet_present (void)
 {
-	return (in_8((u8 *)CONFIG_SYS_PIGGY_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
+	return (in_8((u8 *)CONFIG_SYS_KMBEC_FPGA_BASE + CONFIG_SYS_SLOT_ID_OFF) & 0x80);
 }
 #endif
 
diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c
index ecd19c5..c625b5d 100644
--- a/board/keymile/km83xx/km83xx.c
+++ b/board/keymile/km83xx/km83xx.c
@@ -158,9 +158,9 @@ int board_early_init_r (void)
 		break;
 	}
 	/* enable the PHY on the PIGGY */
-	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
+	setbits (8, (void *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x10003), 0x01);
 	/* enable the Unit LED (green) */
-	setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x00002), 0x01);
+	setbits (8, (void *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x00002), 0x01);
 
 #if defined(CONFIG_SUVD3)
 	/* configure UPMA for APP1 */
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index d9b0380..44dc7a5 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -304,9 +304,9 @@ int board_early_init_r (void)
 {
 	/* setup the UPIOx */
 	/* General Unit Reset disabled, Flash Bank enabled, UnitLed on */
-	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc2);
+	out_8((u8 *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x02), 0xc2);
 	/* SCC4 enable, halfduplex, FCC1 powerdown */
-	out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15);
+	out_8((u8 *)(CONFIG_SYS_KMBEC_FPGA_BASE + 0x03), 0x15);
 	return 0;
 }
 
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index c6a1432..33f2af2 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -102,7 +102,7 @@
  * driver to set the MAC.
 */
 #define CONFIG_CHECK_ETHERNET_PRESENT	1
-#define CONFIG_SYS_SLOT_ID_BASE		CONFIG_SYS_PIGGY_BASE
+#define CONFIG_SYS_SLOT_ID_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
 #define CONFIG_SYS_SLOT_ID_OFF		(0x07)	/* register offset */
 #define CONFIG_SYS_SLOT_ID_MASK		(0x3f)	/* mask for slot ID bits */
 
diff --git a/include/configs/km82xx-common.h b/include/configs/km82xx-common.h
index b28cc99..40a609d 100644
--- a/include/configs/km82xx-common.h
+++ b/include/configs/km82xx-common.h
@@ -274,19 +274,19 @@
 			 PSDMR_WRC_1C                   |\
 			 PSDMR_CL_2)
 
-/* GPIO/PIGGY on CS3 initialization values
+/* UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
 */
-#define CONFIG_SYS_PIGGY_BASE	0x30000000
-#define CONFIG_SYS_PIGGY_SIZE	128
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0x30000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
 
-#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
 			 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 
-#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
 			 ORxG_CSNT | ORxG_ACS_DIV2 |\
 			 ORxG_SCY_3_CLK | ORxG_TRLX )
 
-/* Board FPGA on CS4 initialization values
+/* BFTICU board FPGA on CS4 initialization values
 */
 #define CONFIG_SYS_FPGA_BASE	0x40000000
 #define CONFIG_SYS_FPGA_SIZE	1 /*1KB*/
diff --git a/include/configs/km8321-common.h b/include/configs/km8321-common.h
index a60ee34..19e4ca5 100644
--- a/include/configs/km8321-common.h
+++ b/include/configs/km8321-common.h
@@ -35,9 +35,6 @@
 #define CONFIG_MPC832x		1 /* MPC832x CPU specific */
 #define CONFIG_KM8321		1 /* Keymile PBEC8321 board specific */
 
-#define CONFIG_KM_DEF_NETDEV	\
-	"netdev=eth0\0"
-
 #define CONFIG_KM_DEF_ROOTPATH		\
 	"rootpath=/opt/eldk/ppc_8xx\0"
 
@@ -120,8 +117,8 @@
 
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
-#define CONFIG_SYS_PIGGY_BASE	0xE8000000
-#define	CONFIG_SYS_PIGGY_SIZE	128
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define	CONFIG_SYS_KMBEC_FPGA_SIZE	128
 
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h
index 1be976b..0f835f8 100644
--- a/include/configs/km83xx-common.h
+++ b/include/configs/km83xx-common.h
@@ -120,13 +120,13 @@
 /*
  * PRIO1/PIGGY on the local bus CS1
  */
-#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_PIGGY_BASE
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE /* Window base at flash base */
 #define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001A /* 128MB window size */
 
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_PIGGY_BASE | \
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
 				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 				BR_V)
-#define CONFIG_SYS_OR1_PRELIM		(MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
+#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | /* 128MB */ \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_2 | \
 				OR_GPCM_TRLX | OR_GPCM_EAD)
@@ -213,7 +213,7 @@
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_KMETER1
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_PIGGY_BASE
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
 #endif
 
 #if defined(CONFIG_PCI)
@@ -258,11 +258,11 @@
 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
 
 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
-					BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
-					BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
+				BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
+				BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
 
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index cd64c4a..2e0c342 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -110,9 +110,11 @@
 
 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 
-#define CONFIG_SYS_PIGGY_BASE		0xE8000000
-#define	CONFIG_SYS_PIGGY_SIZE		128
-#define CONFIG_SYS_PAXE_BASE		0xA0000000
+/* PRIO FPGA */
+#define	CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define	CONFIG_SYS_KMBEC_FPGA_SIZE	128
+/* PAXE FPGA */
+#define	CONFIG_SYS_PAXE_BASE		0xA0000000
 #define	CONFIG_SYS_PAXE_SIZE		512
 
 /* EEprom support */
diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h
index 4e6d11f..79cfad1 100644
--- a/include/configs/suvd3.h
+++ b/include/configs/suvd3.h
@@ -23,101 +23,15 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
-#define CONFIG_MPC832x		1 /* MPC832x CPU specific */
 #define CONFIG_SUVD3		1 /* SUVD3 board specific */
 #define CONFIG_HOSTNAME		suvd3
 #define CONFIG_KM_BOARD_NAME   "suvd3"
 
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
-#define CONFIG_KM_DEF_NETDEV	\
-	"netdev=eth0\0"
 
-#define CONFIG_KM_DEF_ROOTPATH		\
-	"rootpath=/opt/eldk/ppc_8xx\0"
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
 
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-#define CONFIG_MISC_INIT_R	1
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH	0x00000006
-#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3 )
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL )
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					 SDRAM_CFG_32_BE | \
-					 SDRAM_CFG_SREN)
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					 CSCONFIG_ODT_WR_CFG | \
-					 CSCONFIG_ROW_BIT_13 | \
-					 CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE		0x47860252
-#define CONFIG_SYS_DDR_MODE2		0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				 (0 << TIMING_CFG0_WWT_SHIFT) | \
-				 (0 << TIMING_CFG0_RRT_SHIFT) | \
-				 (0 << TIMING_CFG0_WRT_SHIFT) | \
-				 (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_50) | \
-				 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
-				 ( 6 << TIMING_CFG1_REFREC_SHIFT) | \
-				 ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				 (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-#define CONFIG_SYS_PIGGY_BASE		0xE8000000
-#define	CONFIG_SYS_PIGGY_SIZE		128
 #define CONFIG_SYS_APP1_BASE		0xA0000000
 #define	CONFIG_SYS_APP1_SIZE		256 // Megabytes
 #define CONFIG_SYS_APP2_BASE		0xB0000000
@@ -127,12 +41,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 
 /*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-/*
  * Init Local Bus Memory Controller:
  *
  * Bank Bus     Machine PortSz  Size  Device
@@ -185,21 +93,6 @@
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
-			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
-#else /* CONFIG_PCI */
-
-/* APP2:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_10 | \
 					BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
@@ -208,10 +101,4 @@
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
 
-#define CONFIG_SYS_IBAT7L	(0)
-#define CONFIG_SYS_IBAT7U	(0)
-#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h
index 1583614..fe9f075 100644
--- a/include/configs/tuda1.h
+++ b/include/configs/tuda1.h
@@ -26,113 +26,20 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
-#define CONFIG_MPC832x		1 /* MPC832x CPU specific */
 #define CONFIG_TUDA1		1 /* TUDA1 board specific */
 #define CONFIG_HOSTNAME		tuda1
 #define CONFIG_KM_BOARD_NAME   "tuda1"
 
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
-#define CONFIG_KM_DEF_NETDEV	\
-	"netdev=eth0\0"
 
-#define CONFIG_KM_DEF_ROOTPATH		\
-	"rootpath=/opt/eldk/ppc_8xx\0"
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
 
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-#define CONFIG_MISC_INIT_R	1
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH	0x00000006
-#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL)
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					SDRAM_CFG_32_BE | \
-					SDRAM_CFG_2T_EN | \
-					SDRAM_CFG_SREN)
-
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					CSCONFIG_ODT_WR_CFG | \
-					CSCONFIG_ROW_BIT_13 | \
-					CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE	0x47860252
-#define CONFIG_SYS_DDR_MODE2	0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				 (0 << TIMING_CFG0_WWT_SHIFT) | \
-				 (0 << TIMING_CFG0_RRT_SHIFT) | \
-				 (0 << TIMING_CFG0_WRT_SHIFT) | \
-				 (0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
-				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 (2 << TIMING_CFG1_WRREC_SHIFT) | \
-				 (6 << TIMING_CFG1_REFREC_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 (2 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				 (5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-
-#define CONFIG_SYS_PIGGY_BASE	0xE8000000
-#define	CONFIG_SYS_PIGGY_SIZE	128
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
 #define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */
 #define	CONFIG_SYS_APP2_SIZE	256 /* Megabytes */
 
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
 /*
  * Local Bus Configuration & Clock Setup
  */
@@ -212,22 +119,6 @@
 				BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | \
-			BATL_PP_10 | \
-			BATL_CACHEINHIBIT | \
-			BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
-#else /* CONFIG_PCI */
-
 /* PINC3:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | \
 				BATL_PP_10 | \
@@ -246,6 +137,5 @@
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h
index 44e12f3..af14c79 100644
--- a/include/configs/tuxa1.h
+++ b/include/configs/tuxa1.h
@@ -26,117 +26,20 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_E300		1 /* E300 family */
-#define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
-#define CONFIG_MPC832x		1 /* MPC832x CPU specific */
 #define CONFIG_TUXA1		1 /* TUXA1 board specific */
 #define CONFIG_HOSTNAME		tuxa1
 #define CONFIG_KM_BOARD_NAME   "tuxa1"
 
 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
-#define CONFIG_KM_DEF_NETDEV	\
-	"netdev=eth0\0"
 
-#define CONFIG_KM_DEF_ROOTPATH		\
-	"rootpath=/opt/eldk/ppc_8xx\0"
+/* include common defines/options for all 8321 Keymile boards */
+#include "km8321-common.h"
 
-/* include common defines/options for all 83xx Keymile boards */
-#include "km83xx-common.h"
-
-#define CONFIG_MISC_INIT_R	1
-
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH	0x00000006
-#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
-
-/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
-	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
-	HRCWL_DDR_TO_SCB_CLK_2X1 | \
-	HRCWL_CSB_TO_CLKIN_2X1 | \
-	HRCWL_CORE_TO_CSB_2_5X1 | \
-	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X3 )
-
-#define CONFIG_SYS_HRCW_HIGH (\
-	HRCWH_PCI_AGENT | \
-	HRCWH_PCI_ARBITER_DISABLE | \
-	HRCWH_CORE_ENABLE | \
-	HRCWH_FROM_0X00000100 | \
-	HRCWH_BOOTSEQ_DISABLE | \
-	HRCWH_SW_WATCHDOG_DISABLE | \
-	HRCWH_ROM_LOC_LOCAL_16BIT | \
-	HRCWH_BIG_ENDIAN | \
-	HRCWH_LALE_NORMAL )
-
-#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
-#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
-					SDRAM_CFG_32_BE | \
-					SDRAM_CFG_2T_EN | \
-					SDRAM_CFG_SREN)
-#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
-#define CONFIG_SYS_DDR_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
-				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
-
-#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
-					CSCONFIG_ODT_WR_CFG | \
-					CSCONFIG_ROW_BIT_13 | \
-					CSCONFIG_COL_BIT_10)
-
-#define CONFIG_SYS_DDR_MODE		0x47860252
-#define CONFIG_SYS_DDR_MODE2		0x8080c000
-
-#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
-				(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
-				(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
-				(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
-				(0 << TIMING_CFG0_WWT_SHIFT) | \
-				(0 << TIMING_CFG0_RRT_SHIFT) | \
-				(0 << TIMING_CFG0_WRT_SHIFT) | \
-				(0 << TIMING_CFG0_RWT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_1	((      TIMING_CFG1_CASLAT_50) | \
-				( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
-				( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				( 2 << TIMING_CFG1_WRREC_SHIFT) | \
-				( 6 << TIMING_CFG1_REFREC_SHIFT) | \
-				( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				( 2 << TIMING_CFG1_PRETOACT_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
-				(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
-				(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
-				(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
-				(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
-				(5 << TIMING_CFG2_CPO_SHIFT))
-
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-
-#define	CONFIG_SYS_PIGGY_BASE		0xE8000000
-#define	CONFIG_SYS_PIGGY_SIZE		128
 #define	CONFIG_SYS_LPXF_BASE		0xA0000000    // LPXF
 #define	CONFIG_SYS_LPXF_SIZE		256 // Megabytes
 #define	CONFIG_SYS_PINC2_BASE		0xB0000000    // PINC2
 #define	CONFIG_SYS_PINC2_SIZE		256 // Megabytes
 
-
-/* EEprom support */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
-
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 /*
  * Init Local Bus Memory Controller:
  *
@@ -204,20 +107,6 @@
 				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
-#ifdef CONFIG_PCI
-/* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT6L	CFG_IBAT6L
-#define CFG_DBAT6U	CFG_IBAT6U
-/* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
-			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT7L	CFG_IBAT7L
-#define CFG_DBAT7U	CFG_IBAT7U
-#else /* CONFIG_PCI */
-
 /* PINC2:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \
 					BATL_MEMCOHERENCE)
@@ -231,6 +120,5 @@
 #define CONFIG_SYS_IBAT7U	(0)
 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
-#endif /* CONFIG_PCI */
 
 #endif /* __CONFIG_H */
