From patchwork Tue Mar 8 13:07:36 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aneesh V X-Patchwork-Id: 85982 X-Patchwork-Delegate: s-paulraj@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 88040B70D0 for ; Wed, 9 Mar 2011 00:10:33 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DAA8728112; Tue, 8 Mar 2011 14:09:36 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id R6sUJHGzLbHT; Tue, 8 Mar 2011 14:09:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 231AE280C2; Tue, 8 Mar 2011 14:08:42 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 29EE428086 for ; Tue, 8 Mar 2011 14:08:30 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LdTE+IfK5-ax for ; Tue, 8 Mar 2011 14:08:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 08F9728087 for ; Tue, 8 Mar 2011 14:08:12 +0100 (CET) Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p28D87b2003603 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 8 Mar 2011 07:08:09 -0600 Received: from localhost (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p28D86NW006457; Tue, 8 Mar 2011 18:38:06 +0530 (IST) From: Aneesh V To: u-boot@lists.denx.de Date: Tue, 8 Mar 2011 18:37:36 +0530 Message-Id: <1299589658-30896-9-git-send-email-aneesh@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1299589658-30896-1-git-send-email-aneesh@ti.com> References: <1299589658-30896-1-git-send-email-aneesh@ti.com> Cc: steve@sakoman.com Subject: [U-Boot] [PATCH v2 08/10] armv7: adapt omap4 to the new cache maintenance framework X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de adapt omap4 to the new layered cache maintenance framework Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/omap4/lowlevel_init.S | 18 ++++++++++++++++++ arch/arm/include/asm/arch-omap4/sys_proto.h | 1 - include/configs/omap4_panda.h | 8 +++++--- include/configs/omap4_sdp4430.h | 8 +++++--- 4 files changed, 28 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S index 026dfa4..5e6c16f 100644 --- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S @@ -45,3 +45,21 @@ lowlevel_init: */ bl s_init pop {ip, pc} + +set_pl310_ctrl_reg: + PUSH {r4-r11, lr} @ save registers - ROM code may pollute + @ our registers + LDR r12, =0x102 @ Set PL310 control register - value in R0 + .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 + @ call ROM Code API to set control register + POP {r4-r11, pc} + +.globl v7_outer_cache_enable +v7_outer_cache_enable: + MOV r0, #1 + B set_pl310_ctrl_reg + +.globl v7_outer_cache_disable +v7_outer_cache_disable: + MOV r0, #0 + B set_pl310_ctrl_reg diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 4813e9e..017f216 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -31,7 +31,6 @@ struct omap_sysinfo { void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); -void invalidate_dcache(u32); void set_muxconf_regs(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 8684798..d7abf94 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -45,9 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_NO_L2CACHE 1 - /* Clock Defines */ #define V_OSCK 38400000 /* Clock output from T2 */ #define V_SCLK V_OSCK @@ -234,4 +231,9 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#ifndef CONFIG_SYS_NO_L2CACHE +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 7cc0c13..3d5ffe5 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -46,9 +46,6 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_NO_L2CACHE 1 - /* Clock Defines */ #define V_OSCK 38400000 /* Clock output from T2 */ #define V_SCLK V_OSCK @@ -240,4 +237,9 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) +#ifndef CONFIG_SYS_NO_L2CACHE +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif + #endif /* __CONFIG_H */