diff mbox

[U-Boot,5/5] powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB

Message ID 1299471454-26740-5-git-send-email-galak@kernel.crashing.org
State Accepted
Delegated to: Kumar Gala
Headers show

Commit Message

Kumar Gala March 7, 2011, 4:17 a.m. UTC
From: Poonam Aggrwal <poonam.aggrwal@freescale.com>

Add support for 36-bit address map for NOR, SD, and SPI boot cfgs.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p1_p2_rdb/p1_p2_rdb.c |    3 +
 board/freescale/p1_p2_rdb/tlb.c       |    9 ++--
 boards.cfg                            |   12 +++++
 include/configs/P1_P2_RDB.h           |   75 +++++++++++++++++++++++++++++---
 4 files changed, 88 insertions(+), 11 deletions(-)
diff mbox

Patch

diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index d4b4b68..307c3e2 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -107,6 +107,9 @@  int checkboard (void)
 
 	cpu = gd->cpu;
 	printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
+#ifdef CONFIG_PHYS_64BIT
+	puts ("(36-bit addrmap) \n");
+#endif
 	setbits_be32(&pgpio->gpdir, GPIO_DIR);
 
 /*
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index e54defb..5b88b68 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -25,19 +25,20 @@ 
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
 			0, 0, BOOKE_PAGESZ_4K, 0),
 
diff --git a/boards.cfg b/boards.cfg
index 45c3102..263c1e6 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -509,15 +509,24 @@  MPC8572DS                    powerpc     mpc85xx     mpc8572ds           freesca
 MPC8572DS_36BIT              powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:36BIT
 MPC8572DS_NAND               powerpc     mpc85xx     mpc8572ds           freescale      -           MPC8572DS:NAND
 P1011RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB
+P1011RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,36BIT
+P1011RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,36BIT,SDCARD
+P1011RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,36BIT,SPIFLASH
 P1011RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,NAND
 P1011RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,SDCARD
 P1011RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1011RDB,SPIFLASH
 P1020RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB
+P1020RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,36BIT
+P1020RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,36BIT,SDCARD
+P1020RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,36BIT,SPIFLASH
 P1020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,NAND
 P1020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SDCARD
 P1020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SPIFLASH
 P1022DS                      powerpc     mpc85xx     p1022ds             freescale
 P2010RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB
+P2010RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,36BIT
+P2010RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,36BIT,SDCARD
+P2010RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,36BIT,SPIFLASH
 P2010RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,NAND
 P2010RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,SDCARD
 P2010RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010RDB,SPIFLASH
@@ -525,6 +534,9 @@  P2020DS                      powerpc     mpc85xx     p2020ds             freesca
 P2020DS_36BIT                powerpc     mpc85xx     p2020ds             freescale      -           P2020DS:36BIT
 P2020DS_DDR2                 powerpc     mpc85xx     p2020ds             freescale      -           P2020DS:DDR2
 P2020RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB
+P2020RDB_36BIT               powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,36BIT
+P2020RDB_36BIT_SDCARD        powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,36BIT,SDCARD
+P2020RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,36BIT,SPIFLASH
 P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,NAND
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index d601fcd..9eed1c8 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -30,6 +30,10 @@ 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
 #ifdef CONFIG_P1011RDB
 #define CONFIG_P1011
 #endif
@@ -123,6 +127,11 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_ENABLE_36BIT_PHYS	1
 
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x1fffffff
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
@@ -144,7 +153,11 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS	0xfffe00000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
+#endif
 							/* CCSRBAR */
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
 							/* CONFIG_SYS_IMMR */
@@ -197,13 +210,17 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 #define CONFIG_SYS_FLASH_BASE		0xef000000	/* start of FLASH 16M */
 
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfef000000ull
+#else
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
 
 #define CONFIG_FLASH_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 					BR_PS_16 | BR_V)
 #define CONFIG_FLASH_OR_PRELIM		0xff000ff7
 
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
 
@@ -231,6 +248,18 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000	/* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
 
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
@@ -242,10 +271,20 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
-#define CONFIG_SYS_NAND_BASE		0xfff00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
+
 #define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define NAND_MAX_CHIPS			1
@@ -292,7 +331,11 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_VSC7385_BASE	0xffb00000
 
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
+#else
 #define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+#endif
 
 #define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
 							| BR_PS_8 | BR_V)
@@ -376,24 +419,42 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 #if defined(CONFIG_PCI)
 #define CONFIG_SYS_PCIE2_NAME		"Slot 1"
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#endif
 
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_NAME		"Slot 2"
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc30000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
 
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */