From patchwork Sat Mar 5 16:13:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 85534 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BD057B708B for ; Sun, 6 Mar 2011 03:13:35 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 22DB928082; Sat, 5 Mar 2011 17:13:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QwehGHEQjCqX; Sat, 5 Mar 2011 17:13:32 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 463E02807C; Sat, 5 Mar 2011 17:13:31 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B5E182807C for ; Sat, 5 Mar 2011 17:13:28 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kbArGMZNv74F for ; Sat, 5 Mar 2011 17:13:27 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id 069892807B for ; Sat, 5 Mar 2011 17:13:25 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p25GDHj9004013; Sat, 5 Mar 2011 10:13:17 -0600 From: Kumar Gala To: u-boot@lists.denx.de Date: Sat, 5 Mar 2011 10:13:17 -0600 Message-Id: <1299341597-20276-1-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.5.6.5 Cc: York Sun Subject: [U-Boot] [PATCH] corenet_ds: pick the middle value for all tested timing parameters X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: York Sun For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent. The best values should be picked up from the middle of all working combinations. This patch updates the table with confirmed values tested on Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s, 900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s, 1200MT/s, 1000MT/s. Signed-off-by: York Sun --- board/freescale/corenet_ds/ddr.c | 58 ++++++++++++-------------------------- 1 files changed, 18 insertions(+), 40 deletions(-) diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 6660b01..f8df9d1 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -170,27 +170,16 @@ const board_specific_parameters_t board_specific_parameters[][30] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 333, 4, 5, 7, 0xff, 2, 0}, - {334, 400, 4, 5, 7, 0xff, 2, 0}, - {401, 549, 4, 5, 7, 0xff, 2, 0}, - {550, 680, 4, 5, 7, 0xff, 2, 0}, - {681, 850, 4, 5, 7, 0xff, 2, 0}, - {851, 1050, 4, 5, 7, 0xff, 2, 0}, - {1051, 1250, 4, 5, 8, 0xff, 2, 0}, - {1251, 1350, 4, 5, 9, 0xff, 2, 0}, - { 0, 333, 2, 5, 7, 0xff, 2, 0}, - {334, 400, 2, 5, 7, 0xff, 2, 0}, - {401, 549, 2, 5, 7, 0xff, 2, 0}, - {550, 680, 2, 5, 7, 0xff, 2, 0}, - {681, 850, 2, 5, 7, 0xff, 2, 0}, - {851, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + { 0, 850, 4, 1, 5, 0xff, 2, 0}, + {851, 950, 4, 3, 5, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + { 0, 850, 2, 5, 6, 0xff, 2, 0}, + {851, 950, 2, 5, 7, 0xff, 2, 0}, + {951, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - { 0, 333, 1, 5, 7, 0xff, 2, 0}, - {334, 400, 1, 5, 7, 0xff, 2, 0}, - {401, 549, 1, 5, 7, 0xff, 2, 0}, - {550, 680, 1, 5, 7, 0xff, 2, 0}, - {681, 850, 1, 5, 7, 0xff, 2, 0} }, { @@ -199,27 +188,16 @@ const board_specific_parameters_t board_specific_parameters[][30] = { * lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 333, 4, 5, 7, 0xff, 2, 0}, - {334, 400, 4, 5, 7, 0xff, 2, 0}, - {401, 549, 4, 5, 7, 0xff, 2, 0}, - {550, 680, 4, 5, 7, 0xff, 2, 0}, - {681, 850, 4, 5, 7, 0xff, 2, 0}, - {851, 1050, 4, 5, 7, 0xff, 2, 0}, - {1051, 1250, 4, 5, 8, 0xff, 2, 0}, - {1251, 1350, 4, 5, 9, 0xff, 2, 0}, - { 0, 333, 2, 5, 7, 0xff, 2, 0}, - {334, 400, 2, 5, 7, 0xff, 2, 0}, - {401, 549, 2, 5, 7, 0xff, 2, 0}, - {550, 680, 2, 5, 7, 0xff, 2, 0}, - {681, 850, 2, 5, 7, 0xff, 2, 0}, - {851, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 5, 7, 0xff, 2, 0}, + { 0, 850, 4, 1, 5, 0xff, 2, 0}, + {851, 950, 4, 3, 5, 0xff, 2, 0}, + {951, 1050, 4, 5, 8, 0xff, 2, 0}, + {1051, 1250, 4, 5, 10, 0xff, 2, 0}, + {1251, 1350, 4, 5, 11, 0xff, 2, 0}, + { 0, 850, 2, 5, 6, 0xff, 2, 0}, + {851, 950, 2, 5, 7, 0xff, 2, 0}, + {951, 1050, 2, 5, 7, 0xff, 2, 0}, + {1051, 1250, 2, 4, 6, 0xff, 2, 0}, {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - { 0, 333, 1, 5, 7, 0xff, 2, 0}, - {334, 400, 1, 5, 7, 0xff, 2, 0}, - {401, 549, 1, 5, 7, 0xff, 2, 0}, - {550, 680, 1, 5, 7, 0xff, 2, 0}, - {681, 850, 1, 5, 7, 0xff, 2, 0} } };