From patchwork Wed Mar 2 21:26:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 85169 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B8D861007D6 for ; Thu, 3 Mar 2011 08:27:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 51B77280BE; Wed, 2 Mar 2011 22:26:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3+v216do323Z; Wed, 2 Mar 2011 22:26:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C93A828099; Wed, 2 Mar 2011 22:26:49 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A15E02808A for ; Wed, 2 Mar 2011 22:26:45 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id u7KnvgV7umYQ for ; Wed, 2 Mar 2011 22:26:44 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from VA3EHSOBE008.bigfish.com (va3ehsobe001.messaging.microsoft.com [216.32.180.11]) by theia.denx.de (Postfix) with ESMTPS id 0458F2808F for ; Wed, 2 Mar 2011 22:26:42 +0100 (CET) Received: from mail52-va3-R.bigfish.com (10.7.14.251) by VA3EHSOBE008.bigfish.com (10.7.40.28) with Microsoft SMTP Server id 14.1.225.8; Wed, 2 Mar 2011 21:26:41 +0000 Received: from mail52-va3 (localhost.localdomain [127.0.0.1]) by mail52-va3-R.bigfish.com (Postfix) with ESMTP id AFD0A1900556 for ; Wed, 2 Mar 2011 21:26:40 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:de01egw02.freescale.net; RD:de01egw02.freescale.net; EFVD:NLI Received: from mail52-va3 (localhost.localdomain [127.0.0.1]) by mail52-va3 (MessageSwitch) id 1299101200314957_1741; Wed, 2 Mar 2011 21:26:40 +0000 (UTC) Received: from VA3EHSMHS023.bigfish.com (unknown [10.7.14.236]) by mail52-va3.bigfish.com (Postfix) with ESMTP id 48B82125804E for ; Wed, 2 Mar 2011 21:26:40 +0000 (UTC) Received: from de01egw02.freescale.net (192.88.165.103) by VA3EHSMHS023.bigfish.com (10.7.99.33) with Microsoft SMTP Server (TLS) id 14.1.225.8; Wed, 2 Mar 2011 21:26:38 +0000 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by de01egw02.freescale.net (8.14.3/8.14.3) with ESMTP id p22LQaaL006193 for ; Wed, 2 Mar 2011 14:26:37 -0700 (MST) Received: from localhost.localdomain (mvp-10-214-72-64.am.freescale.net [10.214.72.64]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p22LQYYX018754; Wed, 2 Mar 2011 15:26:35 -0600 (CST) From: York Sun To: Date: Wed, 2 Mar 2011 13:26:33 -0800 Message-ID: <1299101194-22356-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [Patch v3 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 41bad35..06064a5 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -333,6 +333,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, unsigned char acttoact_mclk; /* Last write data pair to read command issue interval (tWTR) */ unsigned char wrtord_mclk; + /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ + const u8 wrrec_table[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps); acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps); @@ -371,6 +374,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); + + wrrec_mclk = wrrec_table[wrrec_mclk - 1]; if (popts->OTF_burst_chop_en) wrrec_mclk += 2; @@ -810,6 +815,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, unsigned int bl; /* BL: Burst Length */ unsigned int wr_mclk; + /* + * DDR_SDRAM_MODE doesn't support 9,11,13,15 + * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 + * for this table + */ + const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; const unsigned int mclk_ps = get_memory_clk_period_ps(); int i; @@ -853,13 +864,10 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, * 1=fast exit DLL on (tXP) */ dll_on = 1; + wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; - if (wr_mclk >= 12) - wr = 6; - else if (wr_mclk >= 9) - wr = 5; - else - wr = wr_mclk - 4; + wr = wr_table[wr_mclk - 5]; + dll_rst = 0; /* dll no reset */ mode = 0; /* normal mode */