From patchwork Wed Mar 2 18:50:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 85128 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4D8A21007D4 for ; Thu, 3 Mar 2011 05:50:56 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 06ACD2808D; Wed, 2 Mar 2011 19:50:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id l8PdxZoHmH2M; Wed, 2 Mar 2011 19:50:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1652128087; Wed, 2 Mar 2011 19:50:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A151F28086 for ; Wed, 2 Mar 2011 19:50:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L5nb5qv78KtT for ; Wed, 2 Mar 2011 19:50:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from TX2EHSOBE007.bigfish.com (tx2ehsobe004.messaging.microsoft.com [65.55.88.14]) by theia.denx.de (Postfix) with ESMTPS id 0514A28085 for ; Wed, 2 Mar 2011 19:50:48 +0100 (CET) Received: from mail82-tx2-R.bigfish.com (10.9.14.240) by TX2EHSOBE007.bigfish.com (10.9.40.27) with Microsoft SMTP Server id 14.1.225.8; Wed, 2 Mar 2011 18:50:47 +0000 Received: from mail82-tx2 (localhost.localdomain [127.0.0.1]) by mail82-tx2-R.bigfish.com (Postfix) with ESMTP id B6DC110C0216 for ; Wed, 2 Mar 2011 18:50:46 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h) X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:az33egw02.freescale.net; RD:az33egw02.freescale.net; EFVD:NLI Received: from mail82-tx2 (localhost.localdomain [127.0.0.1]) by mail82-tx2 (MessageSwitch) id 1299091846611188_17939; Wed, 2 Mar 2011 18:50:46 +0000 (UTC) Received: from TX2EHSMHS012.bigfish.com (unknown [10.9.14.254]) by mail82-tx2.bigfish.com (Postfix) with ESMTP id 927221A7004D for ; Wed, 2 Mar 2011 18:50:46 +0000 (UTC) Received: from az33egw02.freescale.net (192.88.158.103) by TX2EHSMHS012.bigfish.com (10.9.99.112) with Microsoft SMTP Server (TLS) id 14.1.225.8; Wed, 2 Mar 2011 18:50:45 +0000 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by az33egw02.freescale.net (8.14.3/8.14.3) with ESMTP id p22IohB8026958 for ; Wed, 2 Mar 2011 11:50:44 -0700 (MST) Received: from localhost.localdomain (mvp-10-214-72-64.am.freescale.net [10.214.72.64]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p22Iof71014994; Wed, 2 Mar 2011 12:50:42 -0600 (CST) From: York Sun To: Date: Wed, 2 Mar 2011 10:50:40 -0800 Message-ID: <1299091841-14594-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH 1/2] powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 28 ++++++++++++++++++++++++---- 1 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 41bad35..52bbe76 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -371,6 +371,21 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8; wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps); + + switch (wrrec_mclk) { /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ + case 9: + wrrec_mclk = 10; + break; + case 11: + wrrec_mclk = 12; + break; + case 13: + wrrec_mclk = 14; + break; + case 16: + wrrec_mclk = 16; + break; + } if (popts->OTF_burst_chop_en) wrrec_mclk += 2; @@ -854,12 +869,17 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, */ dll_on = 1; wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps; - if (wr_mclk >= 12) - wr = 6; + if (wr_mclk >= 15) + wr = 0; /* 16 cycles */ + else if (wr_mclk >= 13) + wr = 7; /* 14 cycles */ + else if (wr_mclk >= 11) + wr = 6; /* 12 cycles */ else if (wr_mclk >= 9) - wr = 5; + wr = 5; /* 10 cycles */ else - wr = wr_mclk - 4; + wr = wr_mclk - 4; /* 5~8 cycles */ + dll_rst = 0; /* dll no reset */ mode = 0; /* normal mode */