From patchwork Sat Feb 12 15:07:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Janssen X-Patchwork-Id: 82924 X-Patchwork-Delegate: info@emk-elektronik.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 363F0B712B for ; Sun, 13 Feb 2011 02:08:06 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BEF11281BC; Sat, 12 Feb 2011 16:07:56 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id s6gNw0N-QYGN; Sat, 12 Feb 2011 16:07:56 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 25056281DE; Sat, 12 Feb 2011 16:07:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10461281BC for ; Sat, 12 Feb 2011 16:07:52 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gzjNOsl01zIs for ; Sat, 12 Feb 2011 16:07:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtpq1.gn.mail.iss.as9143.net (smtpq1.gn.mail.iss.as9143.net [212.54.34.164]) by theia.denx.de (Postfix) with ESMTP id 04A04281FD for ; Sat, 12 Feb 2011 16:07:44 +0100 (CET) Received: from [212.54.34.140] (helo=smtp9.gn.mail.iss.as9143.net) by smtpq1.gn.mail.iss.as9143.net with esmtp (Exim 4.71) (envelope-from ) id 1PoH4Z-000710-T7; Sat, 12 Feb 2011 16:07:43 +0100 Received: from 5419b2be.cm-5-2c.dynamic.ziggo.nl ([84.25.178.190] helo=localhost.localdomain) by smtp9.gn.mail.iss.as9143.net with esmtp (Exim 4.71) (envelope-from ) id 1PoH4X-0000aJ-CL; Sat, 12 Feb 2011 16:07:41 +0100 From: Marcel Janssen To: u-boot@lists.denx.de Date: Sat, 12 Feb 2011 16:07:42 +0100 Message-Id: <1297523262-19811-1-git-send-email-korgull@home.nl> X-Mailer: git-send-email 1.7.3.4 To: u-boot@lists.denx.de X-ZiggoSMTP-MailScanner-Information: Please contact the ISP for more information X-ZiggoSMTP-MailScanner-ID: 1PoH4X-0000aJ-CL X-ZiggoSMTP-MailScanner: Found to be clean X-ZiggoSMTP-MailScanner-SpamCheck: geen spam, SpamAssassin (niet cached, score=1.719, vereist 5, ALL_TRUSTED -1.00, BAYES_00 -1.90, RDNS_DYNAMIC 0.98, TO_NO_BRKTS_DIRECT 3.48, TW_DW 0.08, TW_PD 0.08) X-ZiggoSMTP-MailScanner-SpamScore: s X-ZiggoSMTP-MailScanner-From: korgull@home.nl Subject: [U-Boot] [PATCH 4/4] add icnova sam9g45 board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Marcel Signed-off-by: Marcel --- Makefile | 4 + board/in-circuit/icnova/Makefile | 54 ++++++ board/in-circuit/icnova/at91_nand.c | 131 +++++++++++++++ board/in-circuit/icnova/config.mk | 1 + board/in-circuit/icnova/flash2x8.c | 242 +++++++++++++++++++++++++++ board/in-circuit/icnova/icnova_arm.c | 259 +++++++++++++++++++++++++++++ board/in-circuit/icnova/nand.h | 2 + board/in-circuit/icnova/u-boot.lds | 73 ++++++++ include/configs/icnova_sam9g45.h | 305 ++++++++++++++++++++++++++++++++++ 9 files changed, 1071 insertions(+), 0 deletions(-) create mode 100644 board/in-circuit/icnova/Makefile create mode 100644 board/in-circuit/icnova/at91_nand.c create mode 100644 board/in-circuit/icnova/config.mk create mode 100644 board/in-circuit/icnova/flash2x8.c create mode 100644 board/in-circuit/icnova/icnova_arm.c create mode 100644 board/in-circuit/icnova/nand.h create mode 100644 board/in-circuit/icnova/u-boot.lds create mode 100644 include/configs/icnova_sam9g45.h diff --git a/Makefile b/Makefile index 05b404d..c3f72d5 100644 --- a/Makefile +++ b/Makefile @@ -887,6 +887,10 @@ pm9g45_config : unconfig @mkdir -p $(obj)include @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91 +icnova_sam9g45_config : unconfig + @mkdir -p $(obj)include + @$(MKCONFIG) -a icnova_sam9g45 arm arm926ejs icnova in-circuit at91 + SBC35_A9G20_NANDFLASH_config \ SBC35_A9G20_EEPROM_config \ SBC35_A9G20_config : unconfig diff --git a/board/in-circuit/icnova/Makefile b/board/in-circuit/icnova/Makefile new file mode 100644 index 0000000..00e1e2c --- /dev/null +++ b/board/in-circuit/icnova/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# (C) 2008 - 2010 Benjamin Tietz, In-Circuit benjamin.tietz@in-circuit.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk +include $(TOPDIR)/include/config.mk + +LIB := $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o flash.o + +COBJS := icnova_arm.o flash2x8.o +ifdef CONFIG_CMD_NAND +COBJS += at91_nand.o +endif + +COBJS-y += $(COBJS) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +# $(obj).depend +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/in-circuit/icnova/at91_nand.c b/board/in-circuit/icnova/at91_nand.c new file mode 100644 index 0000000..87e3b2e --- /dev/null +++ b/board/in-circuit/icnova/at91_nand.c @@ -0,0 +1,131 @@ +/* + * (C) 2010 + * Benjamin Tietz, In-Circuit + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * hardware specific access to control-lines + */ + +#define CFG_NAND_ALE 21 +#define CFG_NAND_CLE 22 +#define MASK_ALE (1 << CFG_NAND_ALE) +#define MASK_CLE (1 << CFG_NAND_CLE) +#define CFG_NAND_CE AT91_PIN_PC8 +#define CFG_NAND_RDY AT91_PIN_PC11 + +static void icnova_arm9_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(CFG_NAND_CE, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int icnova_arm9_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(CFG_NAND_RDY); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; +#ifdef CONFIG_SYS_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->cmd_ctrl = icnova_arm9_nand_hwcontrol; + nand->dev_ready = icnova_arm9_nand_ready; + nand->chip_delay = 20; + + return 0; +} + +void icnova_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(8) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(28) | AT91_SMC_NCS_WRPULSE_(20) | + AT91_SMC_NRDPULSE_(28) | AT91_SMC_NCS_RDPULSE_(20)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(36) | AT91_SMC_NRDCYCLE_(36)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(3)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CFG_NAND_RDY, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CFG_NAND_CE, 1); +} + diff --git a/board/in-circuit/icnova/config.mk b/board/in-circuit/icnova/config.mk new file mode 100644 index 0000000..9d3c5ae --- /dev/null +++ b/board/in-circuit/icnova/config.mk @@ -0,0 +1 @@ +CONFIG_SYS_TEXT_BASE = 0x73f00000 diff --git a/board/in-circuit/icnova/flash2x8.c b/board/in-circuit/icnova/flash2x8.c new file mode 100644 index 0000000..53190c4 --- /dev/null +++ b/board/in-circuit/icnova/flash2x8.c @@ -0,0 +1,242 @@ +/* + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#ifndef CONFIG_ICNOVA_ARM9 +#include +#include +#else +#define dcache_flush_unlocked() while(0) +#define sync_write_buffer() while(0) +#define uncached(addr) addr +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +flash_info_t flash_info[1]; + +static void flash_identify(uint16_t *flash, flash_info_t *info) +{ + unsigned long flags; + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + + writew(0xaaaa, flash + 0x555); + writew(0x5555, flash + 0xaaa); + writew(0x9090, flash + 0x555); + info->flash_id = readl(flash); + writew(0xf0f0, flash); + + readw(flash); + + if (flags) + enable_interrupts(); +} + +#if CONFIG_SYS_FLASH_SECT > CONFIG_SYS_MAX_FLASH_SECT +# error Flash has more sectors than allowed at max +#endif + +unsigned long flash_init(void) +{ + unsigned long addr; + unsigned int i; + + flash_info[0].size = CONFIG_SYS_FLASH_SIZE; + flash_info[0].sector_count = CONFIG_SYS_FLASH_SECT; + + flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); + + for (i=0, addr =0; + i < CONFIG_SYS_MAX_FLASH_SECT; + i++,addr+=(CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT)) + flash_info[0].start[i] = addr; + + return CONFIG_SYS_FLASH_SIZE; +} + +void flash_print_info(flash_info_t *info) +{ + int i; + printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n", + info->flash_id >> 16, info->flash_id & 0xffff); + printf("Size: %ld MB in %d sectors\n", + info->size >> 10, info->sector_count); + for(i=0; i s_last) + || (s_last >= info->sector_count)) { + puts("Error: first and/or last sector out of range\n"); + return ERR_INVAL; + } + + for (i = s_first; i < s_last; i++) + if (info->protect[i]) { + printf("Error: sector %d is protected\n", i); + return ERR_PROTECTED; + } + + fb = (uint16_t *)uncached(info->start[0]); + + dcache_flush_unlocked(); + + for (i = s_first; (i <= s_last) && !ctrlc(); i++) { + printf("Erasing sector %3d...", i); + + sb = (uint16_t *)uncached(info->start[i]); + + flags = disable_interrupts(); + + start_time = get_timer(0); + + /* Unlock sector */ + writew(0xaaaa, fb + 0x555); + writew(0x7070, sb); + + /* Erase sector */ + writew(0xaaaa, fb + 0x555); + writew(0x5555, fb + 0xaaa); + writew(0x8080, fb + 0x555); + writew(0xaaaa, fb + 0x555); + writew(0x5555, fb + 0xaaa); + writew(0x3030, sb); + + /* Wait for completion */ + ret = ERR_OK; + do { + /* TODO: Timeout */ + status = readw(sb); + } while ((status != 0xffff) /*&& !(status & 0x2828)*/); + + writew(0xf0f0, fb); + + /* + * Make sure the command actually makes it to the bus + * before we re-enable interrupts. + */ + readw(fb); + + if (flags) + enable_interrupts(); + + if (status != 0xffff) { + printf("Flash erase error at address 0x%p: 0x%02x\n", + sb, status); + ret = ERR_PROG_ERROR; + break; + } + } + + if (ctrlc()) + printf("User interrupt!\n"); + + return ERR_OK; +} + +int write_buff(flash_info_t *info, uchar *src, + ulong addr, ulong count) +{ + unsigned long flags; + uint16_t *base, *p, *s, *end; + uint16_t word, status, status1; + int ret = ERR_OK; + + if (addr < info->start[0] + || (addr + count) > (info->start[0] + info->size) + || (addr + count) < addr) { + puts("Error: invalid address range\n"); + return ERR_INVAL; + } + + if (addr & 1 || count & 1 || (unsigned int)src & 1) { + puts("Error: misaligned source, destination or count\n"); + return ERR_ALIGN; + } + + base = (uint16_t *)uncached(info->start[0]); + end = (uint16_t *)uncached(addr + count); + + flags = disable_interrupts(); + + dcache_flush_unlocked(); + sync_write_buffer(); + + for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src; + p < end && !ctrlc(); p++, s++) { + word = *s; + + writew(0xaaaa, base + 0x555); + writew(0x5555, base + 0xaaa); + writew(0xa0a0, base + 0x555); + writew(word, p); + + sync_write_buffer(); + + /* Wait for completion */ + status1 = readw(p); + do { + /* TODO: Timeout */ + status = status1; + status1 = readw(p); + } while (((status ^ status1) & 0x4040) /* toggled */ + /*&& !(status1 & 0x2828)*/); /* error bits */ + + /* + * We'll need to check once again for toggle bit + * because the toggle bit may stop toggling as I/O5 + * changes to "1" (ref at49bv642.pdf p9) + */ + status1 = readw(p); + status = readw(p); + if ((status ^ status1) & 0x4040) { + printf("Flash write error at address 0x%p: " + "0x%02x != 0x%02x\n", + p, status,word); + ret = ERR_PROG_ERROR; + writew(0xf0f0, base); + readw(base); + break; + } + + writew(0xf0f0, base); + readw(base); + } + + if (flags) + enable_interrupts(); + + return ret; +} diff --git a/board/in-circuit/icnova/icnova_arm.c b/board/in-circuit/icnova/icnova_arm.c new file mode 100644 index 0000000..6b68a6e --- /dev/null +++ b/board/in-circuit/icnova/icnova_arm.c @@ -0,0 +1,259 @@ +/* + * (C) 2011 Marcel Janssen, Admesy B.V. + * (C) 2010 Benjamin Tietz, In-Circuit + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_USBD_DFU +#include +#endif +//#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include +#endif +#include +#include "nand.h" + +#if defined(CONFIG_USB_GADGET_ATMEL_USBA) && !defined(CONFIG_USB_GADGET) +#error "Need CONFIG_USB_GADGET when CONFIG_USB_GADGET_ATMEL_USBA enabled" +#endif +int dfu_loop(void); + +DECLARE_GLOBAL_DATA_PTR; +char bootbuf[20]; + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +struct platform_data brd = { + .board = { + //.vbus_pin = AT91_PIN_PC9,// AT91_PIN_PC0, }, + .vbus_pin = AT91_PIN_PC0, + .pullup_pin = 1, + }, + .udc_clk = AT91SAM9G45_ID_UDPHS, +}; +#endif + +#ifdef CONFIG_MACB +static void icnova_arm9_macb_hw_init(void) +{ + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 + * ERX2 (PA8) => PHY ADDR2 + * ERX3 (PA9) => PHY ADDR3 + * ECRS (PA29) => PHY ADDR4 => PHYADDR = 0x0 + * ECOL (PA30) => full MII interface + * ERXER (PA16) => no repeater + * ETXCLK (PA17) => no isolate + */ + unsigned long phy_mask = 0; + /* Reset and pdwn-pins */ + unsigned long rst = pin_to_mask(AT91_PIN_PA27); + unsigned long pdwn = 0; + phy_mask = pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA8) | + pin_to_mask(AT91_PIN_PA9) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13) | + pin_to_mask(AT91_PIN_PA29) | + pin_to_mask(AT91_PIN_PA30) | + pin_to_mask(AT91_PIN_PA16) | + pin_to_mask(AT91_PIN_PA17); + /* Reset and pdwn-pins */ + rst = pin_to_mask(AT91_PIN_PA26); + pdwn = pin_to_mask(AT91_PIN_PA25); + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); + /* + * Set up Pins + */ + writel(rst | pdwn | phy_mask, + pin_to_controller(AT91_PIN_PA0) + PIO_PER); + writel(rst | pdwn | phy_mask, + pin_to_controller(AT91_PIN_PA0) + PIO_OER); + writel(rst | pdwn | phy_mask, + pin_to_controller(AT91_PIN_PA0) + PIO_CODR); + udelay(1000); + writel(rst, + pin_to_controller(AT91_PIN_PA0) + PIO_SODR); + udelay(500000); + // phy-mask will be resetted by internal hardware + +#if 0 + rstc = readl(AT91_BASE_SYS + AT91_RSTC_MR); + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_BASE_SYS + AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + writel(AT91_BASE_SYS + AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(readl(AT91_BASE_SYS + AT91_RSTC_SR) & AT91_RSTC_NRSTL)) + asm("nop"); + + /* Restore NRST value */ + writel(AT91_BASE_SYS + AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); +#endif + + at91_macb_hw_init(); + +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard (void) +{ + char myboard = 0; +#ifdef CONFIG_ICNOVA_ARM9 + printf ("Board : SAM9G45oem\n"); +#endif + printf ("------------------------\n"); + printf("memory \n"); + printf("SDRAM base 0x%08x\n",CONFIG_SYS_SDRAM_BASE); + printf("NAND base 0x%08x\n",CONFIG_SYS_NAND_BASE); + printf("NOR base 0x%08x\n",CONFIG_SYS_FLASH_BASE); + printf("ENV addr 0x%08x\n",CONFIG_ENV_ADDR); + printf ("------------------------\n"); + printf("Interfaces \n"); + #ifdef CONFIG_MACB + printf("Ethernet\n"); + #endif + #ifdef CONFIG_USB_ATMEL + printf("USB host\n"); + #endif + #ifdef CONFIG_USB_GADGET + printf("USB gadget : "); + #ifdef CONFIG_USBD_DFU + printf("DFU\n"); + #endif + #ifdef CONFIG_USB_ETHER + printf("CDC\n"); + #endif + #endif + printf ("------------------------\n"); + printf ("\n"); + return 0; +} +#endif + + +#ifdef CONFIG_CMD_USB +static void at91sam9g45_usb_hw_init(void) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + + at91_set_gpio_output(AT91_PIN_PC9, 0); + at91_set_gpio_output(AT91_PIN_PC0, 0); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + icnova_nand_hw_init(); +#endif + +#ifdef CONFIG_MACB + icnova_arm9_macb_hw_init(); +#endif + +#ifdef CONFIG_CMD_USB + //usb_init(); + at91sam9g45_usb_hw_init(); +#endif + +#ifdef CONFIG_USBD_DFU + /* don't do this here, do it in update_dfu.c */ + //usba_udc_probe(&brd); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + //eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_GADGET_ATMEL_USBA) + rc = usba_udc_probe(&brd); + if (!rc) + rc = usb_eth_initialize(bis); +#endif + +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); +#endif + + return rc; +} diff --git a/board/in-circuit/icnova/nand.h b/board/in-circuit/icnova/nand.h new file mode 100644 index 0000000..9b0b6ea --- /dev/null +++ b/board/in-circuit/icnova/nand.h @@ -0,0 +1,2 @@ + +void icnova_nand_hw_init(void); diff --git a/board/in-circuit/icnova/u-boot.lds b/board/in-circuit/icnova/u-boot.lds new file mode 100644 index 0000000..0d3b19c --- /dev/null +++ b/board/in-circuit/icnova/u-boot.lds @@ -0,0 +1,73 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss (NOLOAD) : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/icnova_sam9g45.h b/include/configs/icnova_sam9g45.h new file mode 100644 index 0000000..b980cf7 --- /dev/null +++ b/include/configs/icnova_sam9g45.h @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2010 + * Marcel Janssen + * + * based on parts from at91sam9263ek.h + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * Configuation settings for the ICnova SAM9G45 OEM board. + * Moved from In-circuit configuration from u-boot-2009.11 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include + +//#define DEBUG +#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ +#define CONFIG_ICNOVA_ARM9 /* It's an ICnova SAM9G45 OEM boardR */ +#define CONFIG_AT91SAM9G45 /* It's an Atmel AT91SAM9G45 SoC */ +#define CONFIG_AT91FAMILY +#define CONFIG_ARCH_AT91 +#define CONFIG_AT91_LEGACY /* needed for some defines */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* this General purpose register is used to trigger + * u-boot to wait for connection. For example, this can + * be used to upgrade the application image in th efollowing way + * 1) host sets the GPBR via Linux. + * 2) host reboots the device + * 3) u-boot reads the GPBR + * 4) u-boot will wait for new firmware +*/ +#define CONFIG_USE_ATMEL_GPBR1 1 +#define CONFIG_CMD_EDITENV + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOOTDELAY 3 +#define CONFIG_DISPLAY_BOARDINFO /* doesn't work properly yet */ + +/* Command line configuration. */ +#include +#define CONFIG_CMD_ASKENV +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_FLASH +/* support FAT support for mem stick or so */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS + +//#define CONFIG_CMD_PORTIO + +/* Hardware drivers */ +#define CONFIG_AT91_GPIO +#define CONFIG_ATMEL_USART +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 /* USART 3 is DBGU */ + +/* Ethernet */ +#define CONFIG_MACB 1 +//#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +/*env : ethprime - When CONFIG_NET_MULTI is enabled controls which + interface is used first.*/ +#define CONFIG_NET_RETRY_COUNT 20 +/* needed to auto boot from NFS */ +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MACB_SEARCH_PHY 1 +//#define CONFIG_NET_DO_NOT_TRY_ANOTHER 1 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_SYS_RX_ETH_BUFFER 1 + +/* BOOTP options */ +//#define CONFIG_BOOTP_BOOTFILESIZE 1 +//#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +//#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_SUBNETMASK + +/* LED */ +#define CONFIG_STATUS_LED +//#define CONFIG_GPIO_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PA22 /* actually the debug leds on the adb1000 */ +#define CONFIG_GREEN_LED AT91_PIN_PA23 +//#define CONFIG_YELLOW_LED AT91_PIN_PD23 +//#define CONFIG_BLUE_LED AT91_PIN_PD26 + +#define STATUS_LED_RED 0 +#define STATUS_LED_GREEN 1 +//#define STATUS_LED_YELLOW 2 +//#define STATUS_LED_BLUE 3 +/* Red */ +#define STATUS_LED_BIT STATUS_LED_RED +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Green */ +#define STATUS_LED_BIT1 STATUS_LED_GREEN +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Yellow */ +//#define STATUS_LED_BIT2 STATUS_LED_YELLOW +//#define STATUS_LED_STATE2 STATUS_LED_OFF +//#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) +/* Blue */ +//#define STATUS_LED_BIT3 STATUS_LED_BLUE +//#define STATUS_LED_STATE3 STATUS_LED_ON +//#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) +/* Optional value */ +//#define STATUS_LED_BOOT STATUS_LED_BIT + +/* USB Host */ +#define CONFIG_USB_ATMEL +//#define CONFIG_USB_EHCI 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_DOS_PARTITION +#define CONFIG_USB_STORAGE + +/* USB gadget support for Ethernet over USB */ +#define CONFIG_USB_GADGET 1 +#define CONFIG_USB_GADGET_ATMEL_USBA 1 +#define CONFIG_USB_GADGET_DUALSPEED 1 +/* only one of these can be active */ +//#define CONFIG_USB_ETHER 1 +#define CONFIG_USBD_DFU 1 + +#ifdef CONFIG_USBD_DFU +//#define CFG_CONSOLE_IS_IN_ENV 1 +#define CONFIG_USBD_VENDORID 0x23CF /* Admesy */ +#define CONFIG_USBD_PRODUCTID_DFU 0x0100 +#define CONFIG_USBD_MANUFACTURER "Admesy" +#define CONFIG_USBD_PRODUCT_NAME "Admesy ICNOVA adb1000 DFU 001" +#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 4096 is maximum or increase USB_BUFSIZ*/ +#define CONFIG_USBD_DFU_INTERFACE 0 +#define DFU_NUM_ALTERNATES 3 /* 3 partitions */ +#endif + +#ifdef CONFIG_USB_ETHER +#define CONFIG_USBD_MANUFACTURER "Armzone" +#define CONFIG_USBD_PRODUCT_NAME "DFU Bootloader " U_BOOT_VERSION +#define CONFIG_EXTRA_ENV_SETTINGS "usbtty=cdc_acm\0" +#define CONFIG_USBD_DFU_XFER_SIZE 4096 +#define CONFIG_USBD_DFU_INTERFACE 2 +#define CONFIG_USBD_VENDORID 0x1457 /* Linux/NetChip */ +#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */ +#define CONFIG_USBD_PRODUCTID_CDCACM 0x511d /* CDC ACM */ +#define CONFIG_USBNET_MANUFACTURER "usba_udc" // "Atmel AT91SAM9G45" +#define CONFIG_USBNET_DEV_ADDR "00:1f:e5:00:1c:7c" // or set usbnet_devaddr in env +#define CONFIG_USBNET_HOST_ADDR "0a:fa:63:8b:e8:0a" // or set usbnet_hostaddr in env +#define CONFIG_USB_CDC_VENDOR_ID 0x0525 +#define CONFIG_USB_CDC_PRODUCT_ID 0xa4a1 +#define CONFIG_USB_RNDIS_VENDOR_ID 0x0525 +#define CONFIG_USB_RNDIS_PRODUCT_ID 0xa4a2 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#endif + + +/* + * SDRAM: 1 bank, min 32, max 128 MB + * Initialized before u-boot gets started. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_LOAD_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x00400000) +#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) +/* additions for new relocation code, must be added to all boards - U-boot dec-2010 */ +#define CONFIG_SYS_SDRAM_BASE 0x70000000 +#define IRAM_BASE_ADDR 0x00300000 +#define IRAM_SIZE 0x00010000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + +#define CONFIG_SYS_MALLOC_LEN (256*1024) + +/* NAND flash */ +#define CONFIG_CMD_MTDPARTS 1 +#define CONFIG_MTD_DEVICE 1 +#define CONFIG_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 8 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTD, 11 +//#define CONFIG_SYS_NAND_U_BOOT_DST 0x40000000 +//#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +/* NOR flash - holds At91bootstrap (sect 1) + u-boot(sec 2-...) +env (sector7) */ +#define CONFIG_CMD_JFFS2 1 +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_FLASH_SIZE 0x00100000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_SECT 8 +#define CONFIG_SYS_MAX_FLASH_SECT 8 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_SEC 1:0-7 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE (CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_FLASH_SECT) +//#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x000E0000) + +/* auto update of u-boot */ +//#define CONFIG_UPDATE_TFTP 1 +#define CONFIG_UPDATE_TFTP_CMD 1 /* build tftpupdate command instead of autoupdate */ +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_LIBFDT 1 +#define CONFIG_UPDATE_LOAD_ADDR 0x70400000 /* loadaddr overrules this */ +#define CONFIG_UPDATE_TFTP_CNT_MAX 5 +#define CONFIG_UPDATE_TFTP_MSEC_MAX 300 +#define CONFIG_SYS_BOOTMAPSZ + + +/* Some default env stuff */ +#define MTDIDS_DEFAULT "nand0=nand.0" +#define MTDPARTS_DEFAULT "mtdparts=nand.0:2M(kernel),16M(root),-(Data)" +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND +//#define CONFIG_IPADDR "192.168.1.2" +//#define CONFIG_SERVERIP "192.168.1.1" +#define CONFIG_BOOTARGS "root=1F01 rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND "mtdparts default; nand read 0x71000000 nand0,0; bootm 0x71000000" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "Sam9g45> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (16*2048) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif