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UIP:(null); IPVD:NLI; H:az33egw02.freescale.net; RD:az33egw02.freescale.net; EFVD:NLI Received: from mail32-va3 (localhost.localdomain [127.0.0.1]) by mail32-va3 (MessageSwitch) id 1296105601559845_9208; Thu, 27 Jan 2011 05:20:01 +0000 (UTC) Received: from VA3EHSMHS027.bigfish.com (unknown [10.7.14.252]) by mail32-va3.bigfish.com (Postfix) with ESMTP id 80BC023804E; Thu, 27 Jan 2011 05:20:01 +0000 (UTC) Received: from az33egw02.freescale.net (192.88.158.103) by VA3EHSMHS027.bigfish.com (10.7.99.37) with Microsoft SMTP Server (TLS) id 14.1.225.8; Thu, 27 Jan 2011 05:19:59 +0000 Received: from az33smr01.freescale.net (az33smr01.freescale.net [10.64.34.199]) by az33egw02.freescale.net (8.14.3/8.14.3) with ESMTP id p0R5JwJY029182; Wed, 26 Jan 2011 22:19:58 -0700 (MST) Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p0R5Jtl6006657; Wed, 26 Jan 2011 23:19:55 -0600 (CST) From: Mingkai Hu To: Date: Thu, 27 Jan 2011 12:52:44 +0800 Message-ID: <1296103972-2696-7-git-send-email-Mingkai.hu@freescale.com> X-Mailer: git-send-email 1.6.4 In-Reply-To: <1296103972-2696-6-git-send-email-Mingkai.hu@freescale.com> References: <1296103972-2696-1-git-send-email-Mingkai.hu@freescale.com> <1296103972-2696-2-git-send-email-Mingkai.hu@freescale.com> <1296103972-2696-3-git-send-email-Mingkai.hu@freescale.com> <1296103972-2696-4-git-send-email-Mingkai.hu@freescale.com> <1296103972-2696-5-git-send-email-Mingkai.hu@freescale.com> <1296103972-2696-6-git-send-email-Mingkai.hu@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: kim.phillips@freescale.com, daveliu@freescale.com, galak@kernel.crashing.org, Emilian.Medve@freescale.com, ruxandra.radulescu@freescale.com, afleming@freescale.com, dai.haruki@freescale.com, timur@freescale.com Subject: [U-Boot] [PATCH 06/14] powerpc/corenet_ds: Add fman support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Kumar Gala Signed-off-by: Kumar Gala Signed-off-by: Mingkai Hu --- board/freescale/corenet_ds/Makefile | 1 + board/freescale/corenet_ds/corenet_ds.c | 11 +- board/freescale/corenet_ds/eth_p4080.c | 352 +++++++++++++++++++++++++++++++ 3 files changed, 359 insertions(+), 5 deletions(-) create mode 100644 board/freescale/corenet_ds/eth_p4080.c diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 1047d78..a6872ac 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o COBJS-y += ddr.o +COBJS-$(CONFIG_P4080DS) += eth_p4080.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 232dc72..2eadf99 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -32,10 +32,12 @@ #include #include #include +#include extern void pci_of_setup(void *blob, bd_t *bd); #include "../common/ngpixis.h" +#include "../../../drivers/net/fm/dtsec.h" DECLARE_GLOBAL_DATA_PTR; @@ -193,6 +195,8 @@ void board_lmb_reserve(struct lmb *lmb) } #endif +extern void fdt_fixup_p4080ds_enet(void * blob); + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -210,9 +214,6 @@ void ft_board_setup(void *blob, bd_t *bd) #endif fdt_fixup_liodn(blob); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); + fdt_fixup_fman_ethernet(blob); + fdt_fixup_p4080ds_enet(blob); } diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c new file mode 100644 index 0000000..465b07c --- /dev/null +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -0,0 +1,352 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/ngpixis.h" +#include "../../../drivers/net/fm/dtsec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define EMI_NONE 0xffffffff +#define EMI_MASK 0xf0000000 +#define EMI1_RGMII 0x0 +#define EMI1_SLOT3 0x80000000 /* bank1 EFGH */ +#define EMI1_SLOT4 0x40000000 /* bank2 ABCD */ +#define EMI1_SLOT5 0xc0000000 /* bank3 ABCD */ +#define EMI2_SLOT4 0x10000000 /* bank2 ABCD */ +#define EMI2_SLOT5 0x30000000 /* bank3 ABCD */ +#define EMI1_MASK 0xc0000000 +#define EMI2_MASK 0x30000000 + +static int mdio_mux[NUM_FM_PORTS]; + +void mux_mdio_for_fm(enum fm_port port, int fm, int num) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK); + gpioval |= mdio_mux[port]; + + out_be32(&pgpio->gpdat, gpioval); +} + +static u32 find_or_alloc_phandle(void * blob, const char * path, u32 phandle) +{ + int off; + u32 ph = 0; + + path = fdt_get_alias(blob, path); + if (path) { + off = fdt_path_offset(blob, path); + if (off) { + ph = fdt_get_phandle(blob, off); + if ((ph == 0) || (ph == -1)) { + ph = phandle++; + fdt_setprop_cell(blob, off, "linux,phandle", ph); + } + } + } + + return ph; +} + +static void fdt_set_phy_handle(void *fdt, char * prop, phys_addr_t pa, + const char *alias) +{ + int offset; + u32 ph = find_or_alloc_phandle(fdt, alias, fdt_alloc_phandle(fdt)); + + offset = fdt_node_offset_by_compat_reg(fdt, prop, pa); + fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); +} + +/* + * Sets the specified node's status to the value contained in "status" + * If the first character of the specified path is "/" then we use + * alias as a path. Otherwise, we look for an alias of that name + */ +static void fdt_set_node_status(void *fdt, const char *alias, + const char *status) +{ + const char *path = fdt_get_alias(fdt, alias); + + if (!path) + path = alias; + + do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + + if (mdio_mux[port] == EMI1_RGMII) { + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); + } + + if (mdio_mux[port] == EMI1_SLOT3) { + int idx = port - FM2_DTSEC1 + 5; + char phy[16]; + + sprintf(phy, "phy%d_slot3", idx); + + fdt_set_phy_handle(blob, prop, pa, phy); + } +} + +void fdt_fixup_p4080ds_enet(void *fdt) +{ + int i; + + /* + * P4080DS can be configured in many different ways, supporting a number + * of combinations of ethernet devices and phy types. In order to + * have just one device tree for all of those configurations, we fix up + * the tree here. By default, the device tree configures FM1 and FM2 + * for SGMII, and configures XAUI on both 10G interfaces. So we have + * a number of different variables to track: + * + * 1) Whether the device is configured at all. Whichever devices are + * not enabled should be disabled by setting the "status" property + * to "disabled". + * 2) What the PHY interface is. If this is an RGMII connection, + * we should change the "phy-connection-type" property to + * "rgmii" + * 3) Which PHY is being used. Because the MDIO buses are muxed, + * we need to redirect the "phy-handle" property to point at the + * PHY on the right slot/bus. + */ + + /* We've got six MDIO nodes that may or may not need to exist */ + fdt_set_node_status(fdt, "emi1_slot3", "disabled"); + fdt_set_node_status(fdt, "emi1_slot4", "disabled"); + fdt_set_node_status(fdt, "emi1_slot5", "disabled"); + fdt_set_node_status(fdt, "emi2_slot4", "disabled"); + fdt_set_node_status(fdt, "emi2_slot5", "disabled"); + + for (i = 0; i < NUM_FM_PORTS; i++) { + switch(mdio_mux[i]) { + case EMI1_SLOT3: + fdt_set_node_status(fdt, "emi1_slot3", "okay"); + break; + case EMI1_SLOT4: + fdt_set_node_status(fdt, "emi1_slot4", "okay"); + break; + case EMI1_SLOT5: + fdt_set_node_status(fdt, "emi1_slot5", "okay"); + break; + case EMI2_SLOT4: + fdt_set_node_status(fdt, "emi2_slot4", "okay"); + break; + case EMI2_SLOT5: + fdt_set_node_status(fdt, "emi2_slot5", "okay"); + break; + } + } +} + +enum board_slots { + SLOT1 = 1, + SLOT2, + SLOT3, + SLOT4, + SLOT5, + SLOT6, +}; + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + int i; + + u8 lane_to_slot[] = { + SLOT1, /* 0 - Bank 1:A */ + SLOT1, /* 1 - Bank 1:B */ + SLOT2, /* 2 - Bank 1:C */ + SLOT2, /* 3 - Bank 1:D */ + SLOT3, /* 4 - Bank 1:E */ + SLOT3, /* 5 - Bank 1:F */ + SLOT3, /* 6 - Bank 1:G */ + SLOT3, /* 7 - Bank 1:H */ + SLOT6, /* 8 - Bank 1:I */ + SLOT6, /* 9 - Bank 1:J */ + SLOT4, /* 10 - Bank 2:A */ + SLOT4, /* 11 - Bank 2:B */ + SLOT4, /* 12 - Bank 2:C */ + SLOT4, /* 13 - Bank 2:D */ + SLOT5, /* 14 - Bank 3:A */ + SLOT5, /* 15 - Bank 3:B */ + SLOT5, /* 16 - Bank 3:C */ + SLOT5, /* 17 - Bank 3:D */ + }; + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + /* The first 4 GPIOs are outputs to control MDIO bus muxing */ + out_be32(&pgpio->gpdir, EMI_MASK); + + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + +#if (CONFIG_SYS_NUM_FMAN == 2) + fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); +#endif + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch(fm_info_get_enet_if(i)) { + case SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT3: + mdio_mux[i] = EMI1_SLOT3; + break; + case SLOT4: + mdio_mux[i] = EMI1_SLOT4; + break; + case SLOT5: + mdio_mux[i] = EMI1_SLOT5; + break; + }; + break; + case RGMII: + fm_info_set_phy_address(i, 0); + mdio_mux[i] = EMI1_RGMII; + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + int idx = i - FM1_10GEC1, lane, slot; + switch(fm_info_get_enet_if(i)) { + case XAUI: + lane = serdes_get_first_lane(XAUI_FM1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT4: + mdio_mux[i] = EMI2_SLOT4; + break; + case SLOT5: + mdio_mux[i] = EMI2_SLOT5; + break; + }; + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch(fm_info_get_enet_if(i)) { + case SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT3: + mdio_mux[i] = EMI1_SLOT3; + break; + case SLOT4: + mdio_mux[i] = EMI1_SLOT4; + break; + case SLOT5: + mdio_mux[i] = EMI1_SLOT5; + break; + }; + break; + case RGMII: + fm_info_set_phy_address(i, 0); + mdio_mux[i] = EMI1_RGMII; + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + int idx = i - FM2_10GEC1, lane, slot; + switch(fm_info_get_enet_if(i)) { + case XAUI: + lane = serdes_get_first_lane(XAUI_FM2 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + switch (slot) { + case SLOT4: + mdio_mux[i] = EMI2_SLOT4; + break; + case SLOT5: + mdio_mux[i] = EMI2_SLOT5; + break; + }; + break; + default: + break; + } + } +#endif + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +}