From patchwork Thu Jan 20 10:58:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Kushwaha X-Patchwork-Id: 79671 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id BB1A1B6EED for ; Thu, 20 Jan 2011 22:14:14 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 13DB028117; Thu, 20 Jan 2011 12:14:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zGZRSGG9DFu1; Thu, 20 Jan 2011 12:14:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B856128124; Thu, 20 Jan 2011 12:14:10 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 18515280DA for ; Thu, 20 Jan 2011 12:14:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FFQhkC-jzN53 for ; Thu, 20 Jan 2011 12:14:07 +0100 (CET) X-Greylist: delayed 904 seconds by postgrey-1.27 at theia; Thu, 20 Jan 2011 12:14:02 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from DB3EHSOBE006.bigfish.com (db3ehsobe006.messaging.microsoft.com [213.199.154.144]) by theia.denx.de (Postfix) with ESMTPS id 0666128126 for ; Thu, 20 Jan 2011 12:14:02 +0100 (CET) Received: from mail70-db3-R.bigfish.com (10.3.81.244) by DB3EHSOBE006.bigfish.com (10.3.84.26) with Microsoft SMTP Server id 14.1.225.8; Thu, 20 Jan 2011 10:58:57 +0000 Received: from mail70-db3 (localhost.localdomain [127.0.0.1]) by mail70-db3-R.bigfish.com (Postfix) with ESMTP id 88B70840465; Thu, 20 Jan 2011 10:58:57 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bh8275dhz2dh2a8h668h) X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:az33egw02.freescale.net; RD:az33egw02.freescale.net; EFVD:NLI Received: from mail70-db3 (localhost.localdomain [127.0.0.1]) by mail70-db3 (MessageSwitch) id 1295521129512232_10591; Thu, 20 Jan 2011 10:58:49 +0000 (UTC) Received: from DB3EHSMHS001.bigfish.com (unknown [10.3.81.240]) by mail70-db3.bigfish.com (Postfix) with ESMTP id 9DF429F0088; Thu, 20 Jan 2011 10:58:26 +0000 (UTC) Received: from az33egw02.freescale.net (192.88.158.103) by DB3EHSMHS001.bigfish.com (10.3.87.101) with Microsoft SMTP Server (TLS) id 14.1.225.8; Thu, 20 Jan 2011 10:58:15 +0000 Received: from de01smr01.freescale.net (de01smr01.freescale.net [10.208.0.31]) by az33egw02.freescale.net (8.14.3/8.14.3) with ESMTP id p0KAwC8R009170; Thu, 20 Jan 2011 03:58:13 -0700 (MST) Received: from localhost.localdomain ([10.232.14.58]) by de01smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p0KAw7lQ024860; Thu, 20 Jan 2011 04:58:11 -0600 (CST) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by localhost.localdomain (8.13.8/8.13.8) with ESMTP id p0KAw66Z010516; Thu, 20 Jan 2011 16:28:06 +0530 Received: (from prabhakar@localhost) by localhost.localdomain (8.13.8/8.13.8/Submit) id p0KAw5dl010515; Thu, 20 Jan 2011 16:28:05 +0530 From: Prabhakar Kushwaha To: Date: Thu, 20 Jan 2011 16:28:04 +0530 Message-ID: <1295521084-10484-1-git-send-email-prabhakar@freescale.com> X-Mailer: git-send-email 1.6.3.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.net Cc: Kumar Gala , Prabhakar Kushwaha Subject: [U-Boot] [PATCH][v1] powerpc/85xx: Add SERDES support for P1010/P1014 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha Signed-off-by: Kumar Gala --- Changes for v1: Incorporated Wolfgang Denk's comment -- removed volatile Based git://git.denx.de/u-boot-mpc85xx.git (branch master) arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 75 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 5 ++ 3 files changed, 82 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/p1010_serdes.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index b7f51e7..69c43b3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -87,9 +87,11 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o +COBJS-$(CONFIG_P1010) += p1010_serdes.o COBJS-$(CONFIG_P1011) += p1021_serdes.o COBJS-$(CONFIG_P1012) += p1021_serdes.o COBJS-$(CONFIG_P1013) += p1013_serdes.o +COBJS-$(CONFIG_P1014) += p1010_serdes.o COBJS-$(CONFIG_P1020) += p1021_serdes.o COBJS-$(CONFIG_P1021) += p1021_serdes.o COBJS-$(CONFIG_P1022) += p1022_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c new file mode 100644 index 0000000..4524d29 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -0,0 +1,75 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Author: Prabhakar Kushwaha + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include +#include +#include +#include +#include + +#define SRDS1_MAX_LANES 4 +#define SRDS2_MAX_LANES 2 + +static u32 serdes1_prtcl_map, serdes2_prtcl_map; + +static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { + [0x00] = {NONE, NONE, NONE, NONE}, + [0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3}, + [0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, + [0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3}, +}; + +static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { + [0x00] = {NONE, NONE}, + [0x01] = {SATA1, SATA2}, + [0x02] = {SATA1, SATA2}, + [0x03] = {PCIE1, PCIE2}, +}; + + +int is_serdes_configured(enum srds_prtcl device) +{ + int ret = (1 << device) & serdes1_prtcl_map; + + if (ret) + return ret; + + return (1 << device) & serdes2_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } + + if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; + serdes2_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 93a9e6c..7531fdc 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1891,8 +1891,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 #else +#if defined(CONFIG_P1010) +#define MPC85xx_PORDEVSR_IO_SEL 0x00600000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 +#else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 +#endif /* if defined(CONFIG_P1010) */ #endif #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000