diff mbox

[U-Boot] powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC

Message ID 1295422740-14142-1-git-send-email-Dipen.Dudhat@freescale.com
State Accepted
Commit beba93ed05d8cea795bad895b6cc1490004fc242
Delegated to: Kumar Gala
Headers show

Commit Message

Dipen Dudhat Jan. 19, 2011, 7:39 a.m. UTC 
Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cpu.c   |    9 ++++++++-
 arch/powerpc/cpu/mpc85xx/speed.c |    6 +++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

Comments

Kumar Gala Jan. 20, 2011, 4:38 a.m. UTC | #1 
On Jan 19, 2011, at 1:39 AM, Dipen Dudhat wrote:

> Future SoC (like the P1010) replace the LBC controller with the new IFC
> (Integrated Flash Controller) so ensure we properly protect code that is
> related to the LBC.
> 
> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
> Acked-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/cpu.c   |    9 ++++++++-
> arch/powerpc/cpu/mpc85xx/speed.c |    6 +++++-
> 2 files changed, 13 insertions(+), 2 deletions(-)

applied to 85xx

- k
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 2f5a505..700e292 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (X.Xiao@motorola.com)
  *
@@ -166,12 +166,14 @@  int checkcpu (void)
 	}
 #endif
 
+#if defined(CONFIG_FSL_LBC)
 	if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
 		printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
 	} else {
 		printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
 		       sysinfo.freqLocalBus);
 	}
+#endif
 
 #ifdef CONFIG_CPM2
 	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -284,7 +286,10 @@  void mpc85xx_reginfo(void)
 {
 	print_tlbcam();
 	print_laws();
+#if defined(CONFIG_FSL_LBC)
 	print_lbc_regs();
+#endif
+
 }
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
@@ -330,8 +335,10 @@  phys_size_t initdram(int board_type)
 	ddr_enable_ecc(dram_size);
 #endif
 
+#if defined(CONFIG_FSL_LBC)
 	/* Some boards also have sdram on the lbc */
 	lbc_sdram_init();
+#endif
 
 	puts("DDR: ");
 	return dram_size;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..f2aa8d0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
@@ -131,7 +131,9 @@  void get_sys_info (sys_info_t * sysInfo)
 
 #else
 	uint plat_ratio,e500_ratio,half_freqSystemBus;
+#if defined(CONFIG_FSL_LBC)
 	uint lcrr_div;
+#endif
 	int i;
 #ifdef CONFIG_QE
 	u32 qe_ratio;
@@ -168,6 +170,7 @@  void get_sys_info (sys_info_t * sysInfo)
 	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
 
+#if defined(CONFIG_FSL_LBC)
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -193,6 +196,7 @@  void get_sys_info (sys_info_t * sysInfo)
 		/* In case anyone cares what the unknown value is */
 		sysInfo->freqLocalBus = lcrr_div;
 	}
+#endif
 }