From patchwork Mon Jan 10 22:02:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 78252 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 118D1B70B3 for ; Tue, 11 Jan 2011 09:05:01 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2911F281AD; Mon, 10 Jan 2011 23:04:32 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q2Diw2UlEiJw; Mon, 10 Jan 2011 23:04:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2FC22818E; Mon, 10 Jan 2011 23:04:29 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10A7D2814E for ; Mon, 10 Jan 2011 23:04:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KPDQaE5ORDEH for ; Mon, 10 Jan 2011 23:04:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from DB3EHSOBE003.bigfish.com (db3ehsobe003.messaging.microsoft.com [213.199.154.141]) by theia.denx.de (Postfix) with ESMTPS id 0628F2819D for ; Mon, 10 Jan 2011 23:04:13 +0100 (CET) Received: from mail47-db3-R.bigfish.com (10.3.81.240) by DB3EHSOBE003.bigfish.com (10.3.84.23) with Microsoft SMTP Server id 14.1.225.8; Mon, 10 Jan 2011 22:04:13 +0000 Received: from mail47-db3 (localhost.localdomain [127.0.0.1]) by mail47-db3-R.bigfish.com (Postfix) with ESMTP id 42BF517A057B for ; Mon, 10 Jan 2011 22:04:13 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h) X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:az33egw02.freescale.net; RD:az33egw02.freescale.net; EFVD:NLI X-FB-SS: 13, Received: from mail47-db3 (localhost.localdomain [127.0.0.1]) by mail47-db3 (MessageSwitch) id 1294697046931163_28612; Mon, 10 Jan 2011 22:04:06 +0000 (UTC) Received: from DB3EHSMHS004.bigfish.com (unknown [10.3.81.252]) by mail47-db3.bigfish.com (Postfix) with ESMTP id A4EAB85005A for ; Mon, 10 Jan 2011 22:03:13 +0000 (UTC) Received: from az33egw02.freescale.net (192.88.158.103) by DB3EHSMHS004.bigfish.com (10.3.87.104) with Microsoft SMTP Server (TLS) id 14.1.225.8; Mon, 10 Jan 2011 22:03:12 +0000 Received: from az33smr02.freescale.net (az33smr02.freescale.net [10.64.34.200]) by az33egw02.freescale.net (8.14.3/8.14.3) with ESMTP id p0AM39lF024532 for ; Mon, 10 Jan 2011 15:03:10 -0700 (MST) Received: from localhost.localdomain (mvp-10-214-72-67.am.freescale.net [10.214.72.67]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p0AM3215005449; Mon, 10 Jan 2011 16:03:07 -0600 (CST) From: York Sun To: Date: Mon, 10 Jan 2011 14:02:59 -0800 Message-ID: <1294696982-20556-5-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1294696982-20556-1-git-send-email-yorksun@freescale.com> References: <1294696982-20556-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [Patch v3 4/7] mpc85xx: Adding more registers and options X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 10 ++++++++-- arch/powerpc/include/asm/fsl_ddr_sdram.h | 12 ++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 21 ++------------------- board/tqc/tqm85xx/sdram.c | 8 ++++---- 4 files changed, 26 insertions(+), 25 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index e46dcb7..23c87af 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -9,6 +9,7 @@ #include #include #include +#include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -79,6 +80,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + out_be32(&ddr->err_disable, regs->err_disable); + out_be32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) + out_be32(&ddr->debug[i], regs->debug[i]); /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; @@ -93,8 +100,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) && in_be32(&ddr->sdram_cfg) & 0x80000) { /* set DEBUG_1[31] */ - u32 temp = in_be32(&ddr->debug_1); - out_be32(&ddr->debug_1, temp | 1); + setbits_be32(&ddr->debug[0], 1); } #endif diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index c6258db..462e918 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -120,6 +120,11 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; unsigned int ddr_eor; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int debug[32]; } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { @@ -175,6 +180,7 @@ typedef struct memctl_options_s { /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; + unsigned int ap_en; /* address parity enable for RDIMM */ /* Global Timing Parameters */ unsigned int cas_latency_override; @@ -210,6 +216,12 @@ typedef struct memctl_options_s { unsigned int zq_en; /* Write leveling */ unsigned int wrlvl_en; + /* RCW override for RDIMM */ + unsigned int rcw_override; + unsigned int rcw_1; + unsigned int rcw_2; + /* control register 1 */ + unsigned int ddr_cdr1; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 30c64eb..0069d50 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -222,25 +222,8 @@ typedef struct ccsr_ddr { u32 capture_ext_address; /* Error Extended Addr Capture */ u32 err_sbe; /* Single-Bit ECC Error Management */ u8 res11[164]; - u32 debug_1; - u32 debug_2; - u32 debug_3; - u32 debug_4; - u32 debug_5; - u32 debug_6; - u32 debug_7; - u32 debug_8; - u32 debug_9; - u32 debug_10; - u32 debug_11; - u32 debug_12; - u32 debug_13; - u32 debug_14; - u32 debug_15; - u32 debug_16; - u32 debug_17; - u32 debug_18; - u8 res12[184]; + u32 debug[32]; /* debug_1 to debug_32 */ + u8 res12[128]; } ccsr_ddr_t; #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 503c5e5..d2af127 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -220,7 +220,7 @@ long int sdram_setup (int casl) * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data * training */ - ddr->debug_3 |= 0x00000400; + ddr->debug[2] |= 0x00000400; /* * 5. Wait 200 micro-seconds @@ -262,18 +262,18 @@ long int sdram_setup (int casl) /* * 8. Clear D3[21] to re-enable data training */ - ddr->debug_3 &= ~0x00000400; + ddr->debug[2] &= ~0x00000400; /* * 9. Set D2(21) to force data training to run */ - ddr->debug_2 |= 0x00000400; + ddr->debug[1] |= 0x00000400; /* * 10. Poll on D2[21] until it is cleared by hardware */ asm ("sync;isync;msync"); - while (ddr->debug_2 & 0x00000400) + while (ddr->debug[1] & 0x00000400) asm ("eieio"); /*