From patchwork Mon Jan 10 12:33:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dirk Eibach X-Patchwork-Id: 78143 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A2D4AB712A for ; Tue, 11 Jan 2011 00:06:25 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 53161280BE; Mon, 10 Jan 2011 14:06:23 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oyCDfrANZY5h; Mon, 10 Jan 2011 14:06:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4770E280B7; Mon, 10 Jan 2011 14:06:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3A9D8280BC for ; Mon, 10 Jan 2011 14:06:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Alc-hPVrzxSh for ; Mon, 10 Jan 2011 14:06:15 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from sputnik.urmx.de (sputnik.urmx.de [88.198.51.18]) by theia.denx.de (Postfix) with ESMTP id 0B73A280B4 for ; Mon, 10 Jan 2011 14:06:13 +0100 (CET) Received: from mailrelay.gdsys.de (unknown [217.6.197.20]) by sputnik.urmx.de (Postfix) with ESMTP id 168A2601FFED for ; Mon, 10 Jan 2011 13:33:34 +0100 (CET) Received: from mailsgw.gdsys.de (localhost [127.0.0.1]) by mailsgw.gdsys.de (Postfix) with ESMTP id 7523A66E3C for ; Mon, 10 Jan 2011 13:33:34 +0100 (CET) From: Dirk Eibach To: u-boot@lists.denx.de Date: Mon, 10 Jan 2011 13:33:24 +0100 Message-Id: <1294662805-11704-2-git-send-email-eibach@gdsys.de> In-Reply-To: <1294662805-11704-1-git-send-email-eibach@gdsys.de> References: <1294662805-11704-1-git-send-email-eibach@gdsys.de> X-SafeGuard_MailGateway: Version: 5.60.3.10058 SGMG Date: 20110110123334Z X-AntiVirus: checked by AntiVir MailGate (version: 2.0.2-5; AVE: 7.9.4.140; VDF: 7.11.1.63; host: mailrelay) Subject: [U-Boot] [PATCH] ppc4xx: Support multiple FPGAs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add support for multiple FPGAs per board for gdsys 405ep architecture. Signed-off-by: Dirk Eibach --- arch/powerpc/include/asm/global_data.h | 2 +- board/gdsys/405ep/405ep.c | 62 +++++---- board/gdsys/405ep/dlvision-10g.c | 214 ++++++++++++++++++++++++------- board/gdsys/405ep/io.c | 8 +- board/gdsys/405ep/iocon.c | 14 +- board/gdsys/common/Makefile | 1 + board/gdsys/common/fpga.h | 12 +- include/configs/dlvision-10g.h | 33 ++++- include/configs/io.h | 7 +- include/configs/iocon.h | 27 ++++- 10 files changed, 275 insertions(+), 105 deletions(-) diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 4068e85..fb7da21 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -173,7 +173,7 @@ typedef struct global_data { unsigned long kbd_status; #endif #ifdef CONFIG_405EP - unsigned fpga_state; + unsigned fpga_state[CONFIG_SYS_FPGA_COUNT]; #endif #if defined(CONFIG_WD_MAX_RATE) unsigned long long wdt_last; /* trace watch-dog triggering rate */ diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index c2d9455..84ea573 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -39,24 +39,26 @@ DECLARE_GLOBAL_DATA_PTR; -int get_fpga_state(void) +int get_fpga_state(unsigned dev) { - return gd->fpga_state; + return gd->fpga_state[dev]; } -void print_fpga_state(void) +void print_fpga_state(unsigned dev) { - if (gd->fpga_state & FPGA_STATE_DONE_FAILED) + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->fpga_state & FPGA_STATE_REFLECTION_FAILED) + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) puts(" FPGA reflection test failed.\n"); } int board_early_init_f(void) { + unsigned k; unsigned ctr; - gd->fpga_state = 0; + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ mtdcr(UIC0ER, 0x00000000); /* disable all ints */ @@ -87,13 +89,15 @@ int board_early_init_f(void) /* * wait for fpga-done */ -#warning this will not work for dlvision-10g - ctr = 0; - while (!(in_le16((void *)LATCH2_BASE) & 0x0010)) { - udelay(100000); - if (ctr++ > 5) { - gd->fpga_state |= FPGA_STATE_DONE_FAILED; - break; + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!(in_le16((void *)LATCH2_BASE) + & CONFIG_SYS_FPGA_DONE(k))) { + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; + break; + } } } @@ -104,20 +108,24 @@ int board_early_init_f(void) out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); - /* - * wait for fpga out of reset - * fail ungraceful if fpga is not working properly - */ - ctr = 0; - while (1) { - fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN); - if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) == - REFLECTION_TESTPATTERN_INV) - break; - udelay(100000); - if (ctr++ > 5) { - gd->fpga_state |= FPGA_STATE_REFLECTION_FAILED; - break; + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + /* + * wait for fpga out of reset + * fail ungraceful if fpga is not working properly + */ + ctr = 0; + while (1) { + fpga_set_reg(k, CONFIG_SYS_FPGA_RFL_LOW, + REFLECTION_TESTPATTERN); + if (fpga_get_reg(k, CONFIG_SYS_FPGA_RFL_HIGH) == + REFLECTION_TESTPATTERN_INV) + break; + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } } } diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index e704f74..c217dfe 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -28,63 +28,98 @@ #include #include "../common/fpga.h" +#include "../common/osd.h" enum { REG_VERSIONS = 0x0002, - REG_FPGA_FEATURES = 0x0004, - REG_FPGA_VERSION = 0x0006, + REG_FPGA_VERSION = 0x0004, + REG_FPGA_FEATURES = 0x0006, }; enum { - UNITTYPE_CCD_SWITCH = 1, + UNITTYPE_VIDEO_USER = 0, + UNITTYPE_MAIN_USER = 1, + UNITTYPE_VIDEO_SERVER = 2, + UNITTYPE_MAIN_SERVER = 3, }; enum { - HWVER_100 = 0, + HWVER_101 = 0, HWVER_110 = 1, - HWVER_121 = 2, - HWVER_122 = 3, }; -/* - * Check Board Identity: - */ -int checkboard(void) +enum { + AUDIO_NONE = 0, + AUDIO_TX = 1, + AUDIO_RX = 2, + AUDIO_RXTX = 3, +}; + +enum { + SYSCLK_156250 = 2, +}; + +enum { + RAM_NONE = 0, + RAM_DDR2_32 = 1, + RAM_DDR2_64 = 2, +}; + +static void print_fpga_info(unsigned dev) { - char *s = getenv("serial#"); - u16 versions = fpga_get_reg(REG_VERSIONS); - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION); - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES); + u16 versions = fpga_get_reg(dev, REG_VERSIONS); + u16 fpga_version = fpga_get_reg(dev, REG_FPGA_VERSION); + u16 fpga_features = fpga_get_reg(dev, REG_FPGA_FEATURES); unsigned unit_type; unsigned hardware_version; - unsigned feature_channels; - unsigned feature_expansion; - int fpga_state = get_fpga_state(); + unsigned feature_compression; + unsigned feature_rs232; + unsigned feature_audio; + unsigned feature_sysclock; + unsigned feature_ramconfig; + unsigned feature_carrier_speed; + unsigned feature_carriers; + unsigned feature_video_channels; + int fpga_state = get_fpga_state(dev); + + printf("FPGA%d: ", dev); - unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; - feature_channels = fpga_features & 0x007f; - feature_expansion = fpga_features & (1<<15); - - printf("Board: "); - - printf("DLVision 10G"); - if (s != NULL) { - puts(", serial# "); - puts(s); + if (fpga_state + && !((hardware_version == HWVER_101) + && (fpga_state == FPGA_STATE_DONE_FAILED))) { + puts("not available\n"); + print_fpga_state(dev); + return; } - if (fpga_state) { - puts("\nFPGA: not available\n"); - print_fpga_state(); - return 0; - } else - puts("\n "); -#if 0 + unit_type = (versions >> 4) & 0x000f; + hardware_version = versions & 0x000f; + feature_compression = (fpga_features >> 13) & 0x0003; + feature_rs232 = fpga_features & (1<<11); + feature_audio = (fpga_features >> 9) & 0x0003; + feature_sysclock = (fpga_features >> 7) & 0x0003; + feature_ramconfig = (fpga_features >> 5) & 0x0003; + feature_carrier_speed = fpga_features & (1<<4); + feature_carriers = (fpga_features >> 2) & 0x0003; + feature_video_channels = fpga_features & 0x0003; + switch (unit_type) { - case UNITTYPE_CCD_SWITCH: - printf("CCD-Switch"); + case UNITTYPE_VIDEO_USER: + printf("Videochannel Userside"); + break; + + case UNITTYPE_MAIN_USER: + printf("Mainchannel Userside"); + break; + + case UNITTYPE_VIDEO_SERVER: + printf("Videochannel Serverside"); + break; + + case UNITTYPE_MAIN_SERVER: + printf("Mainchannel Serverside"); break; default: @@ -93,22 +128,14 @@ int checkboard(void) } switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); + case HWVER_101: + printf(" HW-Ver 1.01\n"); break; case HWVER_110: printf(" HW-Ver 1.10\n"); break; - case HWVER_121: - printf(" HW-Ver 1.21\n"); - break; - - case HWVER_122: - printf(" HW-Ver 1.22\n"); - break; - default: printf(" HW-Ver %d(not supported)\n", hardware_version); @@ -118,9 +145,98 @@ int checkboard(void) printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); - printf(" %d channel(s)", feature_channels); + printf(" %sRS232", feature_rs232 ? "" : "no "); + + switch (feature_audio) { + case AUDIO_NONE: + printf(", no audio"); + break; + + case AUDIO_TX: + printf(", audio tx"); + break; + + case AUDIO_RX: + printf(", audio rx"); + break; + + case AUDIO_RXTX: + printf(", audio rx+tx"); + break; + + default: + printf(", audio %d(not supported)", feature_audio); + break; + } + + switch (feature_sysclock) { + case SYSCLK_156250: + printf(", clock 156.25 MHz"); + break; + + default: + printf(", clock %d(not supported)", feature_sysclock); + break; + } + + puts(",\n "); + + switch (feature_ramconfig) { + case RAM_NONE: + printf("no RAM"); + break; + + case RAM_DDR2_32: + printf("RAM 32 bit DDR2"); + break; + + case RAM_DDR2_64: + printf("RAM 64 bit DDR2"); + break; + + default: + printf("RAM %d(not supported)", feature_ramconfig); + break; + } + + printf(", %d carrier(s) %s", feature_carriers, + feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); + + printf(", %d video channel(s)\n", feature_video_channels); +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + unsigned k; + char *s = getenv("serial#"); + + printf("Board: "); + + printf("DLVision 10G"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + print_fpga_info(k); + + return 0; +} + +int last_stage_init(void) +{ + unsigned k; + + for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k) + if (!get_fpga_state(k)) + osd_probe(k); - printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); -#endif return 0; } diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index 80877b6..b2c02bf 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -95,9 +95,9 @@ err_out: int checkboard(void) { char *s = getenv("serial#"); - u16 versions = fpga_get_reg(REG_VERSIONS); - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION); - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES); + u16 versions = fpga_get_reg(0, REG_VERSIONS); + u16 fpga_version = fpga_get_reg(0, REG_FPGA_VERSION); + u16 fpga_features = fpga_get_reg(0, REG_FPGA_FEATURES); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; @@ -175,7 +175,7 @@ int last_stage_init(void) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ - fpga_set_reg(REG_QUAD_SERDES_RESET, 0); + fpga_set_reg(0, REG_QUAD_SERDES_RESET, 0); return 0; } diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index ecd6cb2..d5196c1 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -75,9 +75,9 @@ enum { int checkboard(void) { char *s = getenv("serial#"); - u16 versions = fpga_get_reg(REG_VERSIONS); - u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION); - u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES); + u16 versions = fpga_get_reg(0, REG_VERSIONS); + u16 fpga_version = fpga_get_reg(0, REG_FPGA_VERSION); + u16 fpga_features = fpga_get_reg(0, REG_FPGA_FEATURES); unsigned unit_type; unsigned hardware_version; unsigned feature_compression; @@ -214,7 +214,7 @@ int checkboard(void) int last_stage_init(void) { - return osd_probe(); + return osd_probe(0); } /* @@ -222,15 +222,15 @@ int last_stage_init(void) */ void fpga_gpio_set(int pin) { - out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin); + out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin); } void fpga_gpio_clear(int pin) { - out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin); + out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin); } int fpga_gpio_get(int pin) { - return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin; + return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin; } diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 2257037..4c7fc99 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -31,6 +31,7 @@ LIB = $(obj)lib$(VENDOR).o COBJS-$(CONFIG_IO) += miiphybb.o COBJS-$(CONFIG_IOCON) += osd.o +COBJS-$(CONFIG_DLVISION_10G) += osd.o COBJS := $(COBJS-y) SOBJS = diff --git a/board/gdsys/common/fpga.h b/board/gdsys/common/fpga.h index 561a29f..29846b7 100644 --- a/board/gdsys/common/fpga.h +++ b/board/gdsys/common/fpga.h @@ -29,17 +29,17 @@ enum { FPGA_STATE_REFLECTION_FAILED = 1 << 1, }; -int get_fpga_state(void); -void print_fpga_state(void); +int get_fpga_state(unsigned dev); +void print_fpga_state(unsigned dev); -static inline u16 fpga_get_reg(unsigned reg) +static inline u16 fpga_get_reg(unsigned dev, unsigned reg) { - return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg)); + return in_le16((void *)(CONFIG_SYS_FPGA_BASE(dev) + reg)); } -static inline void fpga_set_reg(unsigned reg, u16 val) +static inline void fpga_set_reg(unsigned dev, unsigned reg, u16 val) { - return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val); + return out_le16((void *)(CONFIG_SYS_FPGA_BASE(dev) + reg), val); } #endif diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index dafee1f..64da23d 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -38,6 +38,7 @@ #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ +#define CONFIG_LAST_STAGE_INIT #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ @@ -213,20 +214,31 @@ /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 -/* Memory Bank 1 (FPGA) initialization */ -#define CONFIG_SYS_FPGA_BASE 0x7f100000 +/* Memory Bank 1 (FPGA0) initialization */ +#define CONFIG_SYS_FPGA0_BASE 0x7f100000 #define CONFIG_SYS_EBC_PB1AP 0x02825080 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ #define CONFIG_SYS_EBC_PB1CR 0x7f11a000 +/* Memory Bank 2 (FPGA1) initialization */ +#define CONFIG_SYS_FPGA1_BASE 0x7f200000 +#define CONFIG_SYS_EBC_PB2AP 0x03025080 +/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB2CR 0x7f21a000 + +#define CONFIG_SYS_FPGA_BASE(k) \ + (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) + +#define CONFIG_SYS_FPGA_DONE(k) \ + (k ? 0x2000 : 0x10000) + #define CONFIG_SYS_FPGA_RFL_LOW 0x0000 #define CONFIG_SYS_FPGA_RFL_HIGH 0x007e -/* Memory Bank 2 (FPGA_VID) initialization */ -#define CONFIG_SYS_FPGA_VID_BASE 0x7f200000 -#define CONFIG_SYS_EBC_PB2AP 0x02025080 -/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ -#define CONFIG_SYS_EBC_PB2CR 0x7f21a000 +#define CONFIG_SYS_FPGA_OSD_BASE 0x0200 +#define CONFIG_SYS_FPGA_OSD_MEM 0x0800 + +#define CONFIG_SYS_FPGA_COUNT 2 /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f300000 @@ -239,4 +251,11 @@ #define CONFIG_SYS_LATCH1_RESET 0xffcf #define CONFIG_SYS_LATCH1_BOOT 0xffff +/* + * OSD Setup + */ +#define CONFIG_SYS_ICS8N3QV01 +#define CONFIG_SYS_SIL1178 +#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT + #endif /* __CONFIG_H */ diff --git a/include/configs/io.h b/include/configs/io.h index a66c704..e287ad9 100644 --- a/include/configs/io.h +++ b/include/configs/io.h @@ -229,14 +229,19 @@ #define CONFIG_SYS_EBC_PB1CR 0x7f318000 /* Memory Bank 2 (FPGA) initialization */ -#define CONFIG_SYS_FPGA_BASE 0x7f100000 +#define CONFIG_SYS_FPGA0_BASE 0x7f100000 #define CONFIG_SYS_EBC_PB2AP 0x02025080 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ #define CONFIG_SYS_EBC_PB2CR 0x7f11a000 +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 + #define CONFIG_SYS_FPGA_RFL_LOW 0x0000 #define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe +#define CONFIG_SYS_FPGA_COUNT 1 + /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 #define CONFIG_SYS_EBC_PB3AP 0xa2015480 diff --git a/include/configs/iocon.h b/include/configs/iocon.h index 5e61b11..c713915 100644 --- a/include/configs/iocon.h +++ b/include/configs/iocon.h @@ -131,6 +131,12 @@ int fpga_gpio_get(int pin); #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ /* + * OSD hardware + */ +#define CONFIG_SYS_MPC92469AC +#define CONFIG_SYS_CH7301 + +/* * FLASH organization */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ @@ -231,14 +237,22 @@ int fpga_gpio_get(int pin); #define CONFIG_SYS_EBC_PB1AP 0x92015480 #define CONFIG_SYS_EBC_PB1CR 0xFB858000 -/* Memory Bank 2 (FPGA) initialization */ -#define CONFIG_SYS_FPGA_BASE 0x7f100000 +/* Memory Bank 2 (FPGA0) initialization */ +#define CONFIG_SYS_FPGA0_BASE 0x7f100000 #define CONFIG_SYS_EBC_PB2AP 0x02825080 -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000) +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000) + +#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE +#define CONFIG_SYS_FPGA_DONE(k) 0x0010 #define CONFIG_SYS_FPGA_RFL_LOW 0x0000 #define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe +#define CONFIG_SYS_FPGA_OSD_BASE 0x0100 +#define CONFIG_SYS_FPGA_OSD_MEM 0x0800 + +#define CONFIG_SYS_FPGA_COUNT 1 + /* Memory Bank 3 (Latches) initialization */ #define CONFIG_SYS_LATCH_BASE 0x7f200000 #define CONFIG_SYS_EBC_PB3AP 0x02025080 @@ -249,4 +263,11 @@ int fpga_gpio_get(int pin); #define CONFIG_SYS_LATCH1_RESET 0xffff #define CONFIG_SYS_LATCH1_BOOT 0xffff +/* + * OSD Setup + */ +#define CONFIG_SYS_MPC92469AC +#define CONFIG_SYS_CH7301 +#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT + #endif /* __CONFIG_H */