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Mon, 11 Mar 2024 12:23:14 -0500 From: Tejas Bhumkar To: CC: , , , , , Ashok Reddy Soma Subject: [PATCH 07/19] mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes Date: Mon, 11 Mar 2024 22:52:37 +0530 Message-ID: <0fec67801545a91ff9ee7238986a7ec51b730ced.1710098033.git.tejas.arvind.bhumkar@amd.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: tejas.arvind.bhumkar@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343F:EE_|PH7PR12MB7428:EE_ X-MS-Office365-Filtering-Correlation-Id: 102091d5-74d1-4250-d2df-08dc41eff0b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XFBpbPjJShYTISmsGiaGQU+bxg7PGhFCMDb6z6SOB+/cNXmXnLsxhoveq1hUc3DX1sBg5kU97PaX8FhZqBI3KBvoZ0K5t741tt6b17A1WPUWYm9tGhHR8lgiKo+HlBB2Ju6RwhqqZ8Vfc0eLfv+1Crn4wC8QsOsYOFvHao+fNnxZQfz32dRADP/J8NpbqR7WpdWEkrb5w0+DhZVESMCvmZMDsvpV+RQU7nlbojamFWHOWjpX9c7uhvpsn3xmGs+dln7ESDMNTCYtG69vjak1tS+EE34HS/lDjcGGyKvfAIXunP8qjCW4h/ZwdqYdxiSJoFXdbFSnPJ09pTm7HpCsg30bmg+facrslSbgNjZsxDk0XTTOUHG/LS80zbJKWffYDY89razyyhpoSsVYuSIWnHUWXRWagMV/4bhy6IWT7/rJ1ZLwgAGvWDF0shQwniKU1dahtB++xwKYm6OfEG8G9kGvLHkZyKx/7WxuMRaM/wyGYzUyo64GuP3GWw0QywjGrfo6U6/VsghSHQPMfSDdj4HVhbUBEot61JmEwXTOhiRk3MIKzS5H30flb66a++6c+vogYfd++SGPUSe0duuyhbb2UQ+Jnl1oH+gfqcIWv8smOxIId2YcaOAbJ9on72DrajDhmvrzavtTYIxkgkAT9xKxGad0E/fJuCUq0aFdYrDryMwyhTft+3Dy1trCbG8qJVK1arNAvLbkqm0acpdmL5Ist9KfBSlOICc83Su7oXqrk3Cg8aTOOnjkPBSsu9iP X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(36860700004)(1800799015)(376005)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Mar 2024 17:23:17.0161 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 102091d5-74d1-4250-d2df-08dc41eff0b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7428 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Ashok Reddy Soma Enable mt35xu512aba_fixups for all mt35 series flashes to work in DTR mode, and return after nor->fixups is updated, otherwise it will get overwritten with macronix_octal_fixups. This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table. Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced to instruct the Ospi controller driver to switch to DDR mode. Signed-off-by: Ashok Reddy Soma Co-developed-by: Tejas Bhumkar Signed-off-by: Tejas Bhumkar --- drivers/mtd/spi/spi-nor-core.c | 8 +++++++- drivers/spi/cadence_qspi.c | 2 +- include/spi.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5895b5de09..e8640cbf07 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3975,6 +3975,7 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret; + nor->spi->flags |= SPI_XFER_SET_DDR; *buf = SPINOR_MT_OCT_DTR; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), @@ -4302,8 +4303,13 @@ void spi_nor_set_fixups(struct spi_nor *nor) #endif #ifdef CONFIG_SPI_FLASH_MT35XU - if (!strcmp(nor->info->name, "mt35xu512aba")) + if (!strcmp(nor->info->name, "mt35xu512aba") || + !strcmp(nor->info->name, "mt35xl512aba") || + !strcmp(nor->info->name, "mt35xu01g") || + !strcmp(nor->info->name, "mt35xu02g")) { nor->fixups = &mt35xu512aba_fixups; + return; + } #endif #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index dd6aef9ab5..d312bafd90 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -702,7 +702,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, break; } - if (op->cmd.dtr) + if ((spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr) err = cadence_spi_setup_ddrmode(spi, op); return err; diff --git a/include/spi.h b/include/spi.h index ab51c8428b..ade30fab73 100644 --- a/include/spi.h +++ b/include/spi.h @@ -172,6 +172,7 @@ struct spi_slave { #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) #define SPI_XFER_U_PAGE BIT(4) #define SPI_XFER_STACKED BIT(5) +#define SPI_XFER_SET_DDR BIT(6) /* * Flag indicating that the spi-controller has multi chip select * capability and can assert/de-assert more than one chip select