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[U-Boot] Pull request: u-boot-riscv/master 20200804

Message ID 0b463bf7-c024-4b7b-9b60-eba3f0d1983a@ATCPCS12.andestech.com
State Accepted
Delegated to: Tom Rini
Headers show
Series [U-Boot] Pull request: u-boot-riscv/master 20200804 | expand

Pull-request

git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

Message

Andes Aug. 4, 2020, 1:53 a.m. UTC
Hi Tom,

Please pull some riscv updates:

- add DM based reset driver for SiFive SoC's.

Thanks
Rick

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/714339244

The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397:

  Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 10:25:47 -0400)

are available in the Git repository at:

  git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to ed50d3fae49b9dad58674b6609913beeac824e42:

  configs: reset: fu540: enable dm reset framework for SiFive (2020-08-04 09:19:41 +0800)

----------------------------------------------------------------
Sagar Shrikant Kadam (5):
      dt-bindings: prci: add indexes for reset signals available in prci
      fu540: prci: use common reset indexes defined in binding header
      fu540: dtsi: add reset producer and consumer entries
      sifive: reset: add DM based reset driver for SiFive SoC's
      configs: reset: fu540: enable dm reset framework for SiFive

 arch/riscv/dts/fu540-c000-u-boot.dtsi         |  12 ++++++++++++
 arch/riscv/include/asm/arch-fu540/reset.h     |  13 +++++++++++++
 configs/sifive_fu540_defconfig                |   2 ++
 drivers/clk/sifive/fu540-prci.c               |  90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------
 drivers/reset/Kconfig                         |   9 +++++++++
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sifive.c                  | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/dt-bindings/reset/sifive-fu540-prci.h |  19 +++++++++++++++++++
 8 files changed, 239 insertions(+), 25 deletions(-)
 create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h
 create mode 100644 drivers/reset/reset-sifive.c
 create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h

Comments

Tom Rini Aug. 4, 2020, 8:55 p.m. UTC | #1
On Tue, Aug 04, 2020 at 09:53:04AM +0800, uboot@andestech.com wrote:

> Hi Tom,
> 
> Please pull some riscv updates:
> 
> - add DM based reset driver for SiFive SoC's.
> 
> Thanks
> Rick
> 
> https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/714339244
> 
> The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397:
> 
>   Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 10:25:47 -0400)
> 
> are available in the Git repository at:
> 
>   git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git
> 
> for you to fetch changes up to ed50d3fae49b9dad58674b6609913beeac824e42:
> 
>   configs: reset: fu540: enable dm reset framework for SiFive (2020-08-04 09:19:41 +0800)
> 

Applied to u-boot/master, thanks!