diff mbox

[U-Boot,V3] mpc83xx: fix pcie configuration space read/write

Message ID 000701cbb0c3$4f0f5fb0$6401a8c0@LENOVOE5CA6843
State Superseded
Headers show

Commit Message

Baidu Boy Jan. 10, 2011, 12:38 p.m. UTC
This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is 
connected with switch or we use both of the two pcie controller

Signed-off-by: Baidu Boy <liucai.lfn@gmail.com>
---
Changes for V2:
     - Avoid line wrap in the patch
Changes for V3
	- Add space between ) and {

 arch/powerpc/cpu/mpc83xx/pcie.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 46a706d..8429848 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -46,13 +46,15 @@  static struct {
 #endif
 };
 
+static u8 pcie_index = 0;
+
 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 
 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
 {
 	int bus = PCI_BUS(dev) - hose->first_busno;
 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	pex83xx_t *pex = &immr->pciexp[bus];
+	pex83xx_t *pex = &immr->pciexp[pcie_index];
 	struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
 	u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
 	u32 dev_base = bus << 24 | devfn << 16;
@@ -324,6 +326,8 @@  void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
 		num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
 	}
 
-	for (i = 0; i < num_buses; i++)
+	for (i = 0; i < num_buses; i++) {
+		pcie_index = i;
 		mpc83xx_pcie_init_bus(i, reg[i]);
+	}
 }