Show patches with: Submitter = Yang Xiwen via B4 Relay       |    State = Action Required       |    Archived = No       |   7 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[RFC,2/2] net: dwmac_meson8b: Fix incorrect clock divider setting net: dwmac_meson8b: Fix incorrect ETH0 register assignment - - - - --- 2026-01-13 Yang Xiwen via B4 Relay narmstrong New
[RFC,1/2] net: dwmac_meson8b: replace setbits() with clrsetbits() net: dwmac_meson8b: Fix incorrect ETH0 register assignment - - - - --- 2026-01-13 Yang Xiwen via B4 Relay narmstrong New
[v2,5/5] test: clk: add test for CLK_LAZY_REPARENT clk: support arbitrary clk_register() sequence - - - - --- 2025-12-31 Yang Xiwen via B4 Relay trini New
[v2,4/5] clk: allow assigning parent lazily clk: support arbitrary clk_register() sequence - - 1 - --- 2025-12-31 Yang Xiwen via B4 Relay trini New
[v2,3/5] clk: use clk_get_parent() helper in clk_en(dis)able() clk: support arbitrary clk_register() sequence - - 1 - --- 2025-12-31 Yang Xiwen via B4 Relay trini New
[v2,2/5] clk: add uclass id check to clk_get_parent() clk: support arbitrary clk_register() sequence - - 1 - --- 2025-12-31 Yang Xiwen via B4 Relay trini New
[v2,1/5] drivers: core: device: set new parent when old parent is NULL clk: support arbitrary clk_register() sequence - 1 1 - --- 2025-12-31 Yang Xiwen via B4 Relay trini New