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All the JH7110 based boards can use the DT from upstreaming linux kernel. The v1.3b board device tree is set as the default device tree. Support CONFIG_MULTI_DTB_FIT and the SPL selects the correct U-Boot dtb using the EEPROM information. Note: 1. Mars CM (lite) are missing upstream dts and so are detected but not supported in this series. Users of Mars CM and Mars CM Lite may stay with U-Boot v2024.10 until this is resolved. 2. Property values of network phy0/1 for all JH7110 based boards now follow the upstream dts. Changes since v5: - In patch 2, drop the override of rx-internal-delay-ps on phy0 and phy1. - In patch 5, drop "/delete-property/ motorcomm,tx-clk-10-inverted;" for Mars network phy0. - In patch 8, rename fdt and conf based on the compatible identifier of boards. Changes since v4: - Merge patch 2, 3, 5 into patch 1, ensuring git bisect works. - Add a new patch to sort the list of JH7110 imply statements. - Drop the reparent of clock JH7110_AONCLK_APB_FUNC in patch 4, which is unnecessary and will cause errors in gmac0 initialization. Changes since v3: - Add detection for Milk-V Mars CM (lite) boards in patch 13. Changes since v2: - Drop patch 1, because the riscv of_upstream Makefile is created by Conor in commit 239e4705099c. - Drop phy0 rx delay for milkv u-boot dtsi in patch 9. - Add a Fixes tag for patch 13. - In patch 14, the PCB version is only obtained when the product_id is VF7110. Improve the commit messages. Changes since v1: - Drop patch 12. - Modify patch 11 and add three new patches to support CONFIG_MULTI_DTB_FIT. The SPL selects the correct U-Boot dtb using the EEPROM information. History: v5: https://lore.kernel.org/all/20241119020425.51989-1-hal.feng@starfivetech.com/ v4: https://lore.kernel.org/all/20241111020808.38974-1-hal.feng@starfivetech.com/ v3: https://lore.kernel.org/all/20241105034328.56439-1-hal.feng@starfivetech.com/ v2: https://lore.kernel.org/all/20241028015847.42344-1-hal.feng@starfivetech.com/ v1: https://lore.kernel.org/all/20240930155919.111738-1-hal.feng@starfivetech.com/ Hal Feng (11): dts: starfive: Switch to using upstream DT riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT pcie: starfive: Make the driver compatible with upstream DT riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards board: starfive: spl: Drop the unneeded DT modification code configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 based board DT riscv: dts: jh7110: Support multiple DTBs in a Fit image board: starfive: spl: Fix the wrong use of CONFIG_IS_ENABLED() board: starfive: spl: Support multiple DTBs for JH7110 based boards riscv: cpu: jh7110: Sort the list of imply statements arch/riscv/cpu/jh7110/Kconfig | 19 +- arch/riscv/dts/Makefile | 1 - arch/riscv/dts/jh7110-common-u-boot.dtsi | 198 +++++ arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 7 + .../dts/jh7110-pine64-star64-u-boot.dtsi | 6 + .../jh7110-starfive-visionfive-2-u-boot.dtsi | 117 --- ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 6 + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 6 + .../dts/jh7110-starfive-visionfive-2.dts | 11 - .../dts/jh7110-starfive-visionfive-2.dtsi | 380 --------- arch/riscv/dts/jh7110-u-boot.dtsi | 36 +- arch/riscv/dts/jh7110.dtsi | 761 ------------------ board/starfive/visionfive2/spl.c | 391 +-------- configs/starfive_visionfive2_defconfig | 4 +- drivers/clk/starfive/clk-jh7110-pll.c | 6 +- drivers/clk/starfive/clk-jh7110.c | 44 +- drivers/pci/pcie_starfive_jh7110.c | 59 +- .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------ .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ----- 19 files changed, 358 insertions(+), 2135 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi delete mode 100644 arch/riscv/dts/jh7110.dtsi delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h base-commit: 880fcc49eb40a78ed27ff575aa02034d7bd74e80 Tested-by: Anand Moon