mbox series

[v1,0/5] Add new DDR driver support for Agilex7

Message ID 20230423181124.28077-1-sin.hui.kho@intel.com
Headers show
Series Add new DDR driver support for Agilex7 | expand

Message

sin.hui.kho@intel.com April 23, 2023, 6:11 p.m. UTC 
From: Sin Hui Kho <sin.hui.kho@intel.com>

*** BLURB HERE ***

Sin Hui Kho (5):
  ddr: altera: agilex7: Add SDRAM driver for AGILEX7
  arm: socfpga: agilex7: Add boot scratch register used for DDR driver
  arm: socfpga: soc64: Add F2SDRAM sideband manager base address for
    SOC64
  arm: socfpga: agilex7: Add DDR handoff data support for AGILEX7
  ddr: altera: Add IOSSM mailbox support for DDR driver

 .../include/mach/base_addr_soc64.h            |   1 +
 .../mach-socfpga/include/mach/handoff_soc64.h |  11 +-
 .../include/mach/system_manager_soc64.h       |  19 +-
 arch/arm/mach-socfpga/wrap_handoff_soc64.c    |   4 +
 drivers/ddr/altera/Makefile                   |   1 +
 drivers/ddr/altera/iossm_mailbox.c            | 847 ++++++++++++++++++
 drivers/ddr/altera/iossm_mailbox.h            | 142 +++
 drivers/ddr/altera/sdram_agilex7.c            | 331 +++++++
 drivers/ddr/altera/sdram_soc64.c              |  15 +-
 drivers/ddr/altera/sdram_soc64.h              |   9 +-
 10 files changed, 1373 insertions(+), 7 deletions(-)
 create mode 100644 drivers/ddr/altera/iossm_mailbox.c
 create mode 100644 drivers/ddr/altera/iossm_mailbox.h
 create mode 100644 drivers/ddr/altera/sdram_agilex7.c