[v2,00/17] Add Intel N5X SoC support

This is the 2nd version of patchset to add Intel N5X SoC[1] support.

Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.

Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.

[1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html


Patch status:
Have changes: Patch 1, 4, 5, 7, 11, 12, 13, 15, 17
Other patches unchanged.

Detail changelog can find in commit message.

v1->v2:
--------
Patch 1:
- New patch in n5x series, the change is needed to execute
  'linux_qspi_enable' correctly in ATF boot flow

Patch 4:
- Enabled auto detect the endianness from the magic word
- Merged and simplifying the big and little endian flow

Patch 5:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code

Patch 7:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros

Patch 11:
- Renamed local variable “total_size” to “remaining_size”

Patch 12:
- Move is_ddr_init_skipped and its helper functions to DDR driver and
  converted function to positive checking
- Using GENMASK() macro
- Fixed typo
- Return status of subfunction
- Changed dm to n5x

Patch 13:
- No change on the file. Need review again for this patch.
  common.h need to be included before clock_manager.h.

Patch 15:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
  n5x data accordingly.

Patch 17:
- Move linux_qspi_enable from bootcommand


Siew Chin Lim (16):
  arm: socfpga: Move linux_qspi_enable from bootcommand to
    board_prep_linux function
  arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
  arm: socfpga: Add base address for Intel N5X device
  arm: socfpga: Add handoff data support for Intel N5X device
  drivers: clk: Add clock driver for Intel N5X device
  arm: socfpga: Get clock manager base address for Intel N5X device
  drivers: clk: Add memory clock driver for Intel N5X device
  arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
    clock_manager.h
  arm: socfpga: Add clock manager for Intel N5X device
  arm: socfpga: Changed misc_s10.c to misc_soc64.c
  ddr: altera: Add SDRAM driver for Intel N5X device
  arm: socfpga: Add SPL for Intel N5X device
  board: intel: Add socdk board support for Intel N5X device
  arm: dts: Add base dtsi and devkit dts for Intel N5X device
  include: configs: Add Intel N5X device CONFIGs
  arm: socfpga: Enable Intel N5X device build

Tien Fong Chee (1):
  ddr: socfpga: Enable memory test on memory size less than 1GB

 arch/arm/dts/Makefile                         |    1 +
 arch/arm/dts/socfpga_n5x-u-boot.dtsi          |  101 +
 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi    |   67 +
 arch/arm/dts/socfpga_n5x_socdk.dts            |  243 ++
 arch/arm/mach-socfpga/Kconfig                 |   21 +-
 arch/arm/mach-socfpga/Makefile                |   32 +-
 arch/arm/mach-socfpga/board.c                 |   17 +-
 arch/arm/mach-socfpga/clock_manager_n5x.c     |   80 +
 .../{base_addr_s10.h => base_addr_soc64.h}    |   11 +-
 .../mach-socfpga/include/mach/clock_manager.h |    3 +
 .../include/mach/clock_manager_agilex.h       |    2 -
 .../include/mach/clock_manager_arria10.h      |    1 -
 .../include/mach/clock_manager_gen5.h         |    1 -
 .../include/mach/clock_manager_n5x.h          |   12 +
 .../include/mach/clock_manager_s10.h          |    1 -
 arch/arm/mach-socfpga/include/mach/firewall.h |    6 +
 .../mach-socfpga/include/mach/handoff_soc64.h |   38 +-
 .../include/mach/system_manager_soc64.h       |   10 +-
 arch/arm/mach-socfpga/misc.c                  |    3 +
 .../mach-socfpga/{misc_s10.c => misc_soc64.c} |   12 +-
 arch/arm/mach-socfpga/spl_n5x.c               |   94 +
 arch/arm/mach-socfpga/system_manager_soc64.c  |   18 +-
 arch/arm/mach-socfpga/wrap_handoff_soc64.c    |  126 +-
 board/intel/n5x-socdk/MAINTAINERS             |    7 +
 board/intel/n5x-socdk/Makefile                |    7 +
 board/intel/n5x-socdk/socfpga.c               |    7 +
 configs/socfpga_agilex_atf_defconfig          |    2 +-
 ...tf_defconfig => socfpga_n5x_atf_defconfig} |   13 +-
 ...ex_atf_defconfig => socfpga_n5x_defconfig} |   29 +-
 ...tf_defconfig => socfpga_n5x_vab_defconfig} |   14 +-
 configs/socfpga_stratix10_atf_defconfig       |    2 +-
 drivers/clk/altera/Makefile                   |    4 +-
 drivers/clk/altera/clk-mem-n5x.c              |  136 +
 drivers/clk/altera/clk-mem-n5x.h              |   84 +
 drivers/clk/altera/clk-n5x.c                  |  489 ++++
 drivers/clk/altera/clk-n5x.h                  |  217 ++
 drivers/ddr/altera/Makefile                   |    3 +-
 drivers/ddr/altera/sdram_n5x.c                | 2299 +++++++++++++++++
 drivers/ddr/altera/sdram_soc64.c              |   94 +-
 drivers/ddr/altera/sdram_soc64.h              |    1 +
 include/configs/socfpga_n5x_socdk.h           |   45 +
 include/configs/socfpga_soc64_common.h        |    2 +-
 include/dt-bindings/clock/n5x-clock.h         |   71 +
 43 files changed, 4308 insertions(+), 118 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts
 create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c
 rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%)
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
 rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
 create mode 100644 arch/arm/mach-socfpga/spl_n5x.c
 create mode 100644 board/intel/n5x-socdk/MAINTAINERS
 create mode 100644 board/intel/n5x-socdk/Makefile
 create mode 100644 board/intel/n5x-socdk/socfpga.c
 copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (84%)
 copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_defconfig} (63%)
 copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_vab_defconfig} (82%)
 create mode 100644 drivers/clk/altera/clk-mem-n5x.c
 create mode 100644 drivers/clk/altera/clk-mem-n5x.h
 create mode 100644 drivers/clk/altera/clk-n5x.c
 create mode 100644 drivers/clk/altera/clk-n5x.h
 create mode 100644 drivers/ddr/altera/sdram_n5x.c
 create mode 100644 include/configs/socfpga_n5x_socdk.h
 create mode 100644 include/dt-bindings/clock/n5x-clock.h