From patchwork Wed Mar 31 14:38:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1460588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F9TVK1Mdvz9sW4 for ; Thu, 1 Apr 2021 01:39:34 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0D39C805B4; Wed, 31 Mar 2021 16:39:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id CB181828A4; Wed, 31 Mar 2021 16:39:19 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.1 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3C35780462 for ; Wed, 31 Mar 2021 16:39:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: 38Rc3XNFu3SBLNHnSCmzhpwG5D73p+pbkN9jEYdSSCb63EOP1p49DjqBN7zEAE1cFBnmtUk4Gg Kkjma44dunGg== X-IronPort-AV: E=McAfee;i="6000,8403,9940"; a="189786084" X-IronPort-AV: E=Sophos;i="5.81,293,1610438400"; d="scan'208";a="189786084" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2021 07:39:13 -0700 IronPort-SDR: NZrvwBQIhq2otKvmJda2PxXlYsegqLSm1y0LMXtCHpenNm06Ve/i8lBh7tGM+0kZTLKB88cR7b kOEU1W2g16hg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,293,1610438400"; d="scan'208";a="418706723" Received: from pg-iccf0297.altera.com ([10.104.1.8]) by orsmga008.jf.intel.com with ESMTP; 31 Mar 2021 07:39:10 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v1 00/17] Add Intel N5X SoC support Date: Wed, 31 Mar 2021 22:38:51 +0800 Message-Id: <20210331143908.48211-1-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean This patchset add Intel N5X SoC[1] support. Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in N5X are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. Intel N5X SoC supports legacy boot without ATF, ATF boot, and ATF boot with VAB enabled. [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html Siew Chin Lim (16): arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h arm: socfpga: Add base address for Intel N5X device arm: socfpga: Add handoff data support for Intel N5X device drivers: clk: Add clock driver for Intel N5X device arm: socfpga: Get clock manager base address for Intel N5X device drivers: clk: Add memory clock driver for Intel N5X device arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h arm: socfpga: Add clock manager for Intel N5X device arm: socfpga: Changed misc_s10.c to misc_soc64.c arm: socfpga: Add SDRAM driver helper function for Intel N5X device ddr: altera: Add SDRAM driver for Intel N5X device arm: socfpga: Add SPL for Intel N5X device board: intel: Add socdk board support for Intel N5X device arm: dts: Add base dtsi and devkit dts for Intel N5X device include: configs: Add Intel N5X device CONFIGs arm: socfpga: Enable Intel N5X device build Tien Fong Chee (1): ddr: socfpga: Enable memory test on memory size less than 1GB arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 101 + arch/arm/dts/socfpga_n5x.dtsi | 640 ++++++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67 + arch/arm/dts/socfpga_n5x_socdk.dts | 143 ++ arch/arm/mach-socfpga/Kconfig | 20 +- arch/arm/mach-socfpga/Makefile | 26 +- arch/arm/mach-socfpga/clock_manager_n5x.c | 80 + .../mach/{base_addr_s10.h => base_addr_soc64.h} | 11 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 + .../include/mach/clock_manager_agilex.h | 2 - .../include/mach/clock_manager_arria10.h | 1 - .../mach-socfpga/include/mach/clock_manager_gen5.h | 1 - .../mach-socfpga/include/mach/clock_manager_n5x.h | 12 + .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - arch/arm/mach-socfpga/include/mach/firewall.h | 6 + arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28 + arch/arm/mach-socfpga/include/mach/misc.h | 4 + .../include/mach/system_manager_soc64.h | 10 +- arch/arm/mach-socfpga/misc.c | 3 + arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 79 +- arch/arm/mach-socfpga/spl_n5x.c | 94 + arch/arm/mach-socfpga/wrap_handoff_soc64.c | 40 + board/intel/n5x-socdk/MAINTAINERS | 7 + board/intel/n5x-socdk/Makefile | 7 + board/intel/n5x-socdk/socfpga.c | 7 + configs/socfpga_n5x_atf_defconfig | 77 + configs/socfpga_n5x_defconfig | 65 + configs/socfpga_n5x_vab_defconfig | 79 + drivers/clk/altera/Makefile | 4 +- drivers/clk/altera/clk-mem-n5x.c | 136 ++ drivers/clk/altera/clk-mem-n5x.h | 84 + drivers/clk/altera/clk-n5x.c | 489 +++++ drivers/clk/altera/clk-n5x.h | 217 ++ drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_n5x.c | 2316 ++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 28 +- include/configs/socfpga_n5x_socdk.h | 45 + include/configs/socfpga_soc64_common.h | 2 +- include/dt-bindings/clock/n5x-clock.h | 71 + 40 files changed, 4982 insertions(+), 28 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (51%) create mode 100644 arch/arm/mach-socfpga/spl_n5x.c create mode 100644 board/intel/n5x-socdk/MAINTAINERS create mode 100644 board/intel/n5x-socdk/Makefile create mode 100644 board/intel/n5x-socdk/socfpga.c create mode 100644 configs/socfpga_n5x_atf_defconfig create mode 100644 configs/socfpga_n5x_defconfig create mode 100644 configs/socfpga_n5x_vab_defconfig create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644 drivers/clk/altera/clk-mem-n5x.h create mode 100644 drivers/clk/altera/clk-n5x.c create mode 100644 drivers/clk/altera/clk-n5x.h create mode 100644 drivers/ddr/altera/sdram_n5x.c create mode 100644 include/configs/socfpga_n5x_socdk.h create mode 100644 include/dt-bindings/clock/n5x-clock.h