From patchwork Wed Mar 24 06:19:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1457672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F4yky4Xjwz9sWF for ; Wed, 24 Mar 2021 17:19:54 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5DB118172F; Wed, 24 Mar 2021 07:19:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 92E288006D; Wed, 24 Mar 2021 07:19:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.1 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=no autolearn_force=no version=3.4.2 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 010628006D for ; Wed, 24 Mar 2021 07:19:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: h8IEfiuurBmy25xYoHmnqNKYeq2ujQJOgDECkO7TcjmBMytX2BifqYeZgZmkUH7BamSANPM1ty UdmA7QiloAaQ== X-IronPort-AV: E=McAfee;i="6000,8403,9932"; a="190735951" X-IronPort-AV: E=Sophos;i="5.81,272,1610438400"; d="scan'208";a="190735951" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2021 23:19:42 -0700 IronPort-SDR: JOilCM/Pq1JncHWYDXKveKuKHKZJIO80nQiz1oha75jyr1LyC2rg285C5cwtneNqqGJLcJQ5/G /pzoPDZkOAxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,274,1610438400"; d="scan'208";a="593269745" Received: from pg-iccf0298.altera.com ([10.104.1.32]) by orsmga005.jf.intel.com with ESMTP; 23 Mar 2021 23:19:39 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Simon Glass , Yau Wai Gan , Siew Chin Lim Subject: [v2 0/2] Store QSPI reference clock in kHz for SOCFPGA SOC64 Date: Wed, 24 Mar 2021 14:19:33 +0800 Message-Id: <20210324061935.7306-1-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean This is the 2cd version of patchset to clean up clock manager code and store QSPI reference clock in kHz for SOCFPGA SOC64. This patchset is extracted from "Add Intel Diamond Mesa SoC support" series. We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device and we would like to clean up some code before enable N5X device. Patch status: Have changes: Patch 2 Other patches unchanged. Detail changelog can find in commit message. v1->v2: -------- Patch 2: - Rename mbox_qspi_set_controller_clk_hz function to cm_set_qspi_controller_clk_hz function and move to clock_manager.c. - Remove CLOCK_1K macro from socfpga_soc64_common.h - Sort include file list by alphabetical order in mailbox_s10.c History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/cover/20210315143643.33102-1-elly.siew.chin.lim@intel.com/ The first version of this patchset is extracted from "Add Intel Diamond Mesa SoC support" series. https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin.lim@intel.com/ This patchset has dependency on: -------- 1. arm: socfpga: Move Stratix10 and Agilex SPL common code https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin.lim@intel.com/ 2. Restructure Stratix10 and Agilex handoff code https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly.siew.chin.lim@intel.com/ Siew Chin Lim (2): arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Changed to store QSPI reference clock in kHz arch/arm/mach-socfpga/clock_manager.c | 43 ++++++++++++++++++++-- arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --- arch/arm/mach-socfpga/clock_manager_s10.c | 6 --- arch/arm/mach-socfpga/include/mach/clock_manager.h | 5 +++ .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - .../include/mach/system_manager_soc64.h | 16 +++++++- arch/arm/mach-socfpga/mailbox_s10.c | 17 +++++---- 7 files changed, 69 insertions(+), 25 deletions(-)