From patchwork Wed Dec 2 20:32:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1409961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=nRnxePab; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CmWD24BHsz9sVS for ; Thu, 3 Dec 2020 07:44:08 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4F2CF826E6; Wed, 2 Dec 2020 21:43:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="nRnxePab"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5241F826E3; Wed, 2 Dec 2020 21:43:57 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_PASS autolearn=ham autolearn_force=no version=3.4.2 Received: from esa4.microchip.iphmx.com (esa4.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DFF4082653 for ; Wed, 2 Dec 2020 21:43:51 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1606941832; x=1638477832; h=from:to:cc:subject:date:message-id:mime-version; bh=NWI71HxMYMO1Cr5BBDQSJzZ0S1MVA0vs3Tsu5xjJQPM=; b=nRnxePabVxCgZ2y113TZqm1fjby7/EgNPbmX+H2cwZVZYrfTkuXApz3h bCVIaOW7CEcSYUP2c2nSPcjbMgEkyh7OhHOVceqL/XN5CNCA8ywAPDH92 ptLkuJWAwZzkW3F5KcIwC/xLbcgHjxAbocNfYhfePrblXRTCJfchtvSy3 wzyWb2Ci1Zcb/CQ7gkTT3h8gaI81CW9IQiCILV9WHQHe5aig7UL1jGa17 s5egPUIi3jJzntYlqkq0nSk1PHu6BQclzCarhle3vd8Y+yG7GTXqp1Gpy WD+NLyROryglDEQBBzqmp7Oi+LzsZW+7bDNBX+xsqOgCVYMhniEJo/jcL Q==; IronPort-SDR: BJiG8ULbalA1FjWlaAcVnzyKbfCbV9UgiQP4jKSGCNOmqTbIfSxOw02Ek4A0uSzaR//a9pGh/t kv76jlkMmY8jSDLzA1BRoIeIK1AnVSUKEBDx4+ecoByPKL8s56Xz1YfZXcF1hwiZ9HP6ZuNLud uvPcXmkuvDbZS0BdmNbRiVa36U4ddeUwomGXjRmF0Yc3QqqZyTczgAg7Vkf4s1n7bOcDJPb7SB BEv73LKyfG8FQqjMJKG7VXZ/eBZqO2OP7czTjfDMIRgViyoxsqcJfR55qrMm1impoa0KiSNk2I JRE= X-IronPort-AV: E=Sophos;i="5.78,387,1599548400"; d="scan'208";a="95605504" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Dec 2020 13:43:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 2 Dec 2020 13:43:49 -0700 Received: from padmarao-VirtualBox.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 2 Dec 2020 13:43:44 -0700 From: Padmarao Begari To: , , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v5 0/7] Microchip PolarFire SoC support Date: Thu, 3 Dec 2020 02:02:04 +0530 Message-ID: <20201202203211.2843-1-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id 80cbd731df50b9ab646940ea862b70bcaff37225 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 +++++++++ arch/riscv/include/asm/types.h | 4 + board/microchip/mpfs_icicle/Kconfig | 24 + board/microchip/mpfs_icicle/mpfs_icicle.c | 97 +- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 830 ++++++++++++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/mpfs_clk.c | 127 +++ drivers/clk/microchip/mpfs_clk.h | 19 + drivers/clk/microchip/mpfs_clk_cfg.c | 134 +++ drivers/clk/microchip/mpfs_clk_periph.c | 173 ++++ drivers/net/macb.c | 144 ++- drivers/net/macb.h | 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip,mpfs-clock.h | 45 + 23 files changed, 2068 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h