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[v6,0/9] riscv: Clean up timer drivers

Message ID 20200928145229.449782-1-seanga2@gmail.com
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Series riscv: Clean up timer drivers | expand

Message

Sean Anderson Sept. 28, 2020, 2:52 p.m. UTC
This series cleans up the timer drivers in RISC-V and converts them to DM.

This series needs to be tested! I have only tested it on QEMU and the K210.
Notably, this means that the HiFive and anything Andes is completely untested.

This series depends on [1]. Without that patch, build will fail for sifive
targets.

[1] http://patchwork.ozlabs.org/project/uboot/patch/1600157107-57175-2-git-send-email-bmeng.cn@gmail.com/

Changes in v6:
- Don't compile timer_timebase_fallback if CONFIG_CPU is disabled. This config
  is only disabled on nds32; perhaps it can be enabled in the future? In
  addition, SPL_CPU_SUPPORT should probably be renamed to SPL_CPU

Changes in v5:
- Add test for timer_timebase_fallback
- Don't add a dependency on REGMAP for SIFIVE_FU540_DDR. Instead, depend on Bin
  Meng's patch.
- Remove RISCV_SYSCON_PLMT
- Undo changes to ae350 device trees. They are unnecessary with
  timer_timebase_fallback.

Changes in v4:
- Both the Andes PMLT and Sifive CLINT now fall back on timebase-frequency,
  per discussion with Anup Patel
- Introduce helper function for falling back on timebase-frequency
- Modify RISCV_TIMER KConfig
  - Now depends on RISCV
  - Implied by S-Mode (with or without SPL)
- Rebase
- Remove clock-frequency property from k210 clint binding because we fall
  back on timebase-frequency

Changes in v3:
- Don't initialize the IPI in spl_invoke_opensbi. Further testing has
  revealed it to be unnecessary.
- Rebase

Changes in v2:
- Fix SiFive CLINT not getting tick-rate from rtcclk
- Remove RISCV_RDTIME KConfig option
- Split Kendryte binding changes into their own commit

Sean Anderson (9):
  riscv: Rework riscv timer driver to only support S-mode
  timer: Add helper for drivers using timebase fallback
  timer: Add a test for timer_timebase_fallback
  riscv: Rework Andes PLMT as a UCLASS_TIMER driver
  riscv: Clean up initialization in Andes PLIC
  riscv: Rework Sifive CLINT as UCLASS_TIMER driver
  riscv: clk: Add CLINT clock to kendryte clock driver
  riscv: Update Kendryte device tree for new CLINT driver
  riscv: Update SiFive device tree for new CLINT driver

 arch/riscv/Kconfig                            | 16 -----
 arch/riscv/cpu/ax25/Kconfig                   |  2 +-
 arch/riscv/cpu/fu540/Kconfig                  |  2 +-
 arch/riscv/cpu/generic/Kconfig                |  2 +-
 arch/riscv/dts/fu540-c000-u-boot.dtsi         |  8 ++-
 .../dts/hifive-unleashed-a00-u-boot.dtsi      |  4 ++
 arch/riscv/dts/k210.dtsi                      |  7 +-
 arch/riscv/include/asm/global_data.h          |  3 -
 arch/riscv/include/asm/syscon.h               |  4 +-
 arch/riscv/lib/Makefile                       |  1 -
 arch/riscv/lib/andes_plic.c                   | 58 +++++++---------
 arch/riscv/lib/andes_plmt.c                   | 44 ++++++-------
 arch/riscv/lib/rdtime.c                       | 38 -----------
 arch/riscv/lib/sifive_clint.c                 | 66 ++++++++++---------
 arch/sandbox/dts/test.dts                     |  9 ++-
 arch/sandbox/include/asm/cpu.h                | 11 ++++
 drivers/clk/kendryte/clk.c                    |  4 ++
 drivers/cpu/cpu_sandbox.c                     | 39 +++++++++--
 drivers/timer/Kconfig                         |  4 +-
 drivers/timer/riscv_timer.c                   | 39 +++++------
 drivers/timer/sandbox_timer.c                 |  4 +-
 drivers/timer/timer-uclass.c                  | 31 +++++++++
 include/dt-bindings/clock/k210-sysctl.h       |  1 +
 include/timer.h                               | 15 +++++
 test/dm/timer.c                               | 27 +++++++-
 25 files changed, 254 insertions(+), 185 deletions(-)
 delete mode 100644 arch/riscv/lib/rdtime.c
 create mode 100644 arch/sandbox/include/asm/cpu.h