Message ID | 20200729095636.1077054-1-seanga2@gmail.com |
---|---|
Headers | show |
Series | riscv: Clean up timer drivers | expand |
Hi Sean, On Wed, Jul 29, 2020 at 5:56 PM Sean Anderson <seanga2@gmail.com> wrote: > > This series cleans up the timer drivers in RISC-V and converts them to DM. > > This series depends on [1]. This series needs to be tested! I have only tested > it on QEMU and the K210. Notably, this means that the HiFive and anything Andes > is completely untested. CI for this series is located at [2]. > > [1] https://patchwork.ozlabs.org/project/uboot/list/?series=190862 > [2] https://dev.azure.com/seanga2/u-boot/_build/results?buildId=4 > > Changes in v2: > - Remove RISCV_RDTIME KConfig option > - Split Kendryte binding changes into their own commit > - Fix SiFive CLINT not getting tick-rate from rtcclk This series does not apply to u-boot/master. Please rebase. Regards, Bin