From patchwork Fri May 29 06:03:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pragnesh Patel X-Patchwork-Id: 1300368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=selector1 header.b=A9aoMj2Y; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49YDYB4dGRz9sSr for ; Fri, 29 May 2020 16:04:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E17878116F; Fri, 29 May 2020 08:04:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="A9aoMj2Y"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AD321811F9; Fri, 29 May 2020 08:04:11 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,MSGID_FROM_MTA_HEADER, SPF_HELO_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2061f.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5a::61f]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7E34F810E0 for ; Fri, 29 May 2020 08:04:07 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pragnesh.patel@sifive.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OQNQO6w7v8ZfDLQb2cfVaDIOUZ0Cr4n94NI5HdBlZjLMFYlHiCCXyqMtWmfGUan6yyOC689qoDp1k1WwlC5tlEwMBFSZPq9voZmeqQEp8QsgMQEyIx28tvwc5OBRALAb3FbdlaNQlhTLpaNTMQBRFYjQhC9B7kgsYLZWYPQirNhWnLQHC4lJgw5vj7gKh9m01Y2zN8460jb/pgpuhYMi4UaK8/MnR7rxk7P83k4MRaf3VZHOMOFPOti+VRqzDDcfq3KpQaaa0bRye5Hfchoy+TCCVmPkjNYwTV7il9mpiFh9/0SZ2QRnEDgpYwIxVsXLjkQDNzLnsC2m2kg4zjoxEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OIyfVmn6xRqU9MK8y7o5K6SaTTdIEau33QYT021xdD4=; b=cH70mKt7DnUz18RXQAZymoGBUNbAclBZjbhJjfNrVq5cOQGq+Co4kW8vBRXSQNcCp8hcmG33jAox5SmkWiogcX83gT+7X154vyMw0wa2bvZ2lnIwzN8cXGQfjFy6AJ0uIf0WTpjCe+m/fXoa4uKNb3IxKgRiCGSW2OW1Ab5cbroTBj8rg6zl5yAZnUA9nrw+ffan3EWzcLyhpKTdf1O0kxyYJFCrGXIEZsgE7kLqowe2lI3Rb+/iz8q88YHKTNd+cX83whmP+PygnCXZmMblHAqdQsWkzfTcAG9NC6ku+Y7ktYRMWTB4XBrd/wR6CnmmS65VWOKDjScvuj6hGeRsYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=sifive.com; dmarc=pass action=none header.from=sifive.com; dkim=pass header.d=sifive.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OIyfVmn6xRqU9MK8y7o5K6SaTTdIEau33QYT021xdD4=; b=A9aoMj2YtqAhUsp3sqO7UWykUuHtSrPrTQMCBaoubWkj4Ufy/W098IfRjO3co0pIqAwg13xucz76bSebxE1FMFFD2ZrpmWXbxMQtq2Wz24S5bFS1nr2/fBZR7QKBDgdroXt/TuAtKN1brksGdIA4B15YD5Qk23ixozF0Zz5duYU= Authentication-Results: lists.denx.de; dkim=none (message not signed) header.d=none;lists.denx.de; dmarc=none action=none header.from=sifive.com; Received: from MN2PR13MB2797.namprd13.prod.outlook.com (2603:10b6:208:f2::30) by MN2PR13MB3135.namprd13.prod.outlook.com (2603:10b6:208:135::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.7; Fri, 29 May 2020 06:04:01 +0000 Received: from MN2PR13MB2797.namprd13.prod.outlook.com ([fe80::e50d:b981:362f:58ed]) by MN2PR13MB2797.namprd13.prod.outlook.com ([fe80::e50d:b981:362f:58ed%5]) with mapi id 15.20.3045.015; Fri, 29 May 2020 06:04:01 +0000 From: Pragnesh Patel To: u-boot@lists.denx.de Cc: atish.patra@wdc.com, palmerdabbelt@google.com, bmeng.cn@gmail.com, paul.walmsley@sifive.com, jagan@amarulasolutions.com, anup.patel@wdc.com, sagar.kadam@sifive.com, rick@andestech.com, Pragnesh Patel Subject: [PATCH v13 00/19] RISC-V SiFive FU540 support SPL Date: Fri, 29 May 2020 11:33:20 +0530 Message-Id: <20200529060340.26708-1-pragnesh.patel@sifive.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: LO2P265CA0079.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::19) To MN2PR13MB2797.namprd13.prod.outlook.com (2603:10b6:208:f2::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sachinj2-OptiPlex-7010.open-silicon.com (114.143.65.226) by LO2P265CA0079.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:8::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3045.21 via Frontend Transport; Fri, 29 May 2020 06:03:58 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [114.143.65.226] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 67fa5f9f-a73e-439c-e127-08d803961574 X-MS-TrafficTypeDiagnostic: MN2PR13MB3135: X-LD-Processed: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1,ExtAddr X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:119; X-Forefront-PRVS: 04180B6720 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: my6sn4wTB7pLBrg3pJE3B6OzfzmyuiirUe9bTZXGcqlMDO9Yv/46U+BWfvDe03F4cpcl5A1Bcrs3IgRMUeN5H2jbZptkYk4el0DrFo7T5zkpHwGP8BUIzRo00mfxeCFOX997uh+vYoN+gHwjnB/MmmL5RX9qDV4dI3B36nfNMjtiLreoW8JIyv26qNf97Z8WKqqn110zBmNhcDXQfrpGA3avqFa6dIbcT3ZCx/2VwWvcEDDaetx3zWPo6IVoirAWlDvhSjAK71WTxwhd1O0f1eUrT62+m3Q8ypWhNTf+5wX0leWBM2UXD2jDzsibomTyYGWDy2SkpWwMYHaSXXqXRtDWokMAG4s2+LpOhwO9oG6zGcV//EblWzC7M7Nh4GBj2gZxGA/FgpDwXRRZxvKzOg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MN2PR13MB2797.namprd13.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(6029001)(396003)(39850400004)(136003)(376002)(366004)(346002)(956004)(44832011)(26005)(6506007)(2906002)(52116002)(316002)(5660300002)(1006002)(6666004)(1076003)(86362001)(36756003)(8676002)(107886003)(66476007)(66556008)(2616005)(6916009)(966005)(16526019)(186003)(478600001)(8936002)(83380400001)(4326008)(66946007)(6512007)(6486002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: nES6XK895yh6jJquOyCvEcZ0Rd7ShKheC3LQfpJIaEdjPVv0vv4+YJCAnXS/Vm8qFf/inTtKEWZ2wGyTi+ynG441zk5et3Kgno3VeSLv54xIncvFV302phJYWud+XfZ6abgfk/9Mx95/Z6dVXBMlEDvi1WTQkyR05T56gDW1iHco3JbulbX46Raa0Am0yP6grRDQaveF5FsA6djpHDiwF3vMVGE+myfZvPKkYB83pv9UR3bJOekzALQk3CvoPT8m359uyPrFYXbXM/3VnGr3jdxxvNXOAuQqlMk/wDcYXgO7JzTOjtpKDLscaFw+yY5NOdDXRPk1ybWAs5JVMKJUVcgmnrunUBeslKqsYx3DZzYdX9GIJBWCYKbikPBVJsBwOgTXMQiby3to9JahoBRYYhguv3i1gNHzXynxVDQqzSq/0K5hQIudvxRL71xlR8cHznG5BJjD48sdx16D9aRh1yH5Gj+wohx+OZvSBKIUhIY= X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 67fa5f9f-a73e-439c-e127-08d803961574 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2020 06:04:01.6622 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: U5xADK09YHKjdkJ9HQoAiMDo0hzmjmPHkvfKMUOhLSsYNdGpjw7V01dzV9ExwMbTY1Z1ocSLGYT1uTGripoHlPpVsib5DNU5BfwoPSTkX4Y= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR13MB3135 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean This series add support for SPL to FU540. U-Boot SPL can boot from L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. This series is also available here [1] for testing [1] https://github.com/pragnesh26992/u-boot/tree/spl How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y 2) export OPENSBI= 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) # sudo sgdisk --clear \ > --set-alignment=2 \ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > /dev/sda 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 Changes in v13: - Add a new patch to set the ethernet clock rate (riscv: sifive: dts: fu540: set ethernet clock rate) Changes in v12: - Rebase on mainline U-Boot Added necessary include files which are not part of common header now Remove unnecessary include files drivers/misc/sifive-otp.c +#include +#include board/sifive/fu540/fu540.c -#include +#include board/sifive/fu540/spl.c +#include +#include +#include drivers/ram/sifive/fu540_ddr.c +#include arch/riscv/cpu/fu540/cpu.c -#include +#include arch/riscv/cpu/fu540/spl.c -#include +#include board/sifive/fu540/spl.c -#include +#include +#include +#include - Update commit description for Release ethernet clock reset - Update OpenSBI building section in "doc/board/sifive/fu540.rst" Changes in v11: - Remove TPL related code and OF_PLATDATA from FU540 DDR driver (drivers/ram/sifive/fu540_ddr.c) - Update FU540 doc (doc/board/sifive/fu540.rst) Remove unnecessary print Changes in v10: - Update commit description for ethernet clock reset (https://patchwork.ozlabs.org/patch/1289003) - Update commit description for ddr clock initialization (https://patchwork.ozlabs.org/patch/1289000) Changes in v9: - Remove cache related patches from this series sifive: dts: fu540: Enable L2 Cache in U-Boot (https://patchwork.ozlabs.org/patch/1286705) riscv: sifive: fu540: enable all cache ways from U-Boot proper (https://patchwork.ozlabs.org/patch/1286706) - Rename SiFive DDR driver from sdram_fu540.c to fu540_ddr.c and also do some typo correction in driver - Remove CONFIG_SPL_BUILD for __prci_ddr_release_reset() - Release ethernet clock reset instead of ethernet clock initialization (https://patchwork.ozlabs.org/patch/1286697) - Squash fu540 cpu patches (https://patchwork.ozlabs.org/patch/1286699) (https://patchwork.ozlabs.org/patch/1286700) - Use spl_boot_device() instead of board_boot_order() Changes in v8: - Remove SPL_CRC7_SUPPORT Kconfig option and compile crc7.o when CONFIG_MMC_SPI selected - Add "TODO" in drivers/ram/sifive/sdram_fu540.c - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed - Add 2 new patches sifive: fu540: Add sample SD gpt partition layout (https://patchwork.ozlabs.org/patch/1092) sifive: fu540: Add U-Boot proper sector start (https://patchwork.ozlabs.org/patch/1093) - Remove patch riscv: Enable cpu clock if it is present (https://patchwork.ozlabs.org/patch/1281573) - Update doc/board/sifive/fu540.rst for PLATFORM=generic Changes in v7: - Standardize SD gpt partition layout - Add delay for SiFive OTP driver - Use DM way for corepll and ddrpll - Add new cpu fu540 (arch/riscv/cpu/fu540) - Update document for FU540 (doc/board/sifive/fu540.rst) Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Jagan Teki (2): sifive: fu540: Add sample SD gpt partition layout sifive: fu540: Add U-Boot proper sector start Pragnesh Patel (17): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings riscv: sifive: dts: fu540: add U-Boot dmc node clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add ddr clock initialization clk: sifive: fu540-prci: Release ethernet clock reset riscv: sifive: dts: fu540: set ethernet clock rate riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux riscv: cpu: fu540: Add support for cpu fu540 riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-Boot SPL doc: sifive: fu540: Add description for OpenSBI generic platform arch/riscv/Kconfig | 1 + arch/riscv/cpu/fu540/Kconfig | 15 + arch/riscv/cpu/fu540/Makefile | 11 + arch/riscv/cpu/fu540/cpu.c | 22 + arch/riscv/cpu/fu540/dram.c | 38 + arch/riscv/cpu/fu540/spl.c | 23 + arch/riscv/cpu/u-boot-spl.lds | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 89 + arch/riscv/dts/fu540-c000.dtsi | 37 +- .../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 22 + arch/riscv/dts/hifive-unleashed-a00.dts | 9 + arch/riscv/include/asm/arch-fu540/clk.h | 14 + arch/riscv/include/asm/arch-fu540/gpio.h | 38 + arch/riscv/include/asm/arch-fu540/spl.h | 14 + board/sifive/fu540/Kconfig | 18 +- board/sifive/fu540/Makefile | 4 + board/sifive/fu540/fu540.c | 134 +- board/sifive/fu540/spl.c | 74 + common/spl/Kconfig | 3 +- configs/sifive_fu540_defconfig | 8 + doc/board/sifive/fu540.rst | 135 +- drivers/clk/sifive/fu540-prci.c | 177 +- drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/sifive-otp.c | 275 +++ drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/sifive/Kconfig | 13 + drivers/ram/sifive/Makefile | 6 + drivers/ram/sifive/fu540_ddr.c | 410 +++++ include/configs/sifive-fu540.h | 31 + lib/Makefile | 2 +- 33 files changed, 3018 insertions(+), 106 deletions(-) create mode 100644 arch/riscv/cpu/fu540/Kconfig create mode 100644 arch/riscv/cpu/fu540/Makefile create mode 100644 arch/riscv/cpu/fu540/cpu.c create mode 100644 arch/riscv/cpu/fu540/dram.c create mode 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-ddr.dtsi create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h create mode 100644 board/sifive/fu540/spl.c create mode 100644 drivers/misc/sifive-otp.c create mode 100644 drivers/ram/sifive/Kconfig create mode 100644 drivers/ram/sifive/Makefile create mode 100644 drivers/ram/sifive/fu540_ddr.c