From patchwork Mon Mar 23 20:15:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 1260249 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=yTb10c5u; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48mQcm6yhDz9sNg for ; Tue, 24 Mar 2020 07:16:08 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1315181807; Mon, 23 Mar 2020 21:15:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="yTb10c5u"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 2354B81764; Mon, 23 Mar 2020 21:15:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 046AD80111 for ; Mon, 23 Mar 2020 21:15:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02NKFM2V005384; Mon, 23 Mar 2020 15:15:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584994522; bh=pVUJnIhe6KyXHpNwnDqUaLYFnOtFp+t4iLPVNZhOpeU=; h=From:To:CC:Subject:Date; b=yTb10c5u0NvCpKmPi2jnLpHFkp2OaX4ifmwIravDLi+72bZNTORQ4ZTy87b//HKYs zEhrz6mRNpz3PQ4iiyFEKjKEy0YLpRCwcOJVduBljumf25/DM5MVxlCYw/jlGZQ5M1 BQqd+XwqkaBdCp1Ym+DGHaMonoBzOmOWdk3HO4Wk= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02NKFMHF000966 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 23 Mar 2020 15:15:22 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Mon, 23 Mar 2020 15:15:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Mon, 23 Mar 2020 15:15:22 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02NKFKEf092283; Mon, 23 Mar 2020 15:15:20 -0500 From: Pratyush Yadav To: Jagan Teki , Vignesh Raghavendra CC: Pratyush Yadav , , Sekhar Nori Subject: [PATCH v2 00/16] mtd: spi-nor-core: add xSPI Octal DTR support Date: Tue, 24 Mar 2020 01:45:02 +0530 Message-ID: <20200323201519.20341-1-p.yadav@ti.com> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean Hi, This series adds support for octal DTR flashes in the spi-nor framework, and then adds hooks for the Cypress Semper flash which is an xSPI compliant Octal DTR flash. The Cadence QSPI controller driver is also updated to run in Octal DTR mode. Tested on TI J721e EVM with 1-bit ECC on the Cypress flash on top of u-boot-ti/next. This series depends on [0]. v1 can be found at [1]. [0] cf. <20200224071051.19331-1-p.yadav@ti.com> [0] https://lists.denx.de/pipermail/u-boot/2020-February/401192.html [1] cf. <20200226125606.22684-1-p.yadav@ti.com> [1] https://lists.denx.de/pipermail/u-boot/2020-February/401414.html Changes in v2: - Update the series with comments received on the corresponding kernel series. - Drop the DT properties "spi-rx-dtr" and "spi-tx-dtr". Instead, if later a need is felt to disable DTR in case someone has a board with Octal DTR capable flash but does not support DTR transactions for some reason, a property like "spi-no-dtr" can be added. - Remove mode bits SPI_RX_DTR and SPI_TX_DTR. - Rename 'is_dtr' to 'dtr'. - Make 'dtr' a bitfield. - Reject DTR ops in spi_mem_default_supports_op(). - Perform a Software Reset on flashes that support it when shutting down. - Perform a Software Reset on boot if enabled. - Drop enum 'spi_mem_cmd_ext' and make command opcode u16 instead. Update spi-nor to use the 2-byte command instead of the command extension. Since we still need a "extension type", mode that enum to spi-nor and name it 'spi_nor_cmd_ext'. - Rework hwcaps selection to use supports_op() instead of relying on mode bits. - Fix a build failure when SFDP is not enabled. - Read CFR3V instead of CFR3N in the s28hs setup hook. Reading CFR3N means we need to know beforehand how many dummy cycles are needed. Reading CFR3V doesn't need that because the dummy cycles are exactly the same as the Read ID cycles. So if we can Read ID we can read volatile registers. Pratyush Yadav (16): spi: spi-mem: allow specifying whether an op is DTR or not spi: spi-mem: allow specifying a command's extension spi: cadence-qspi: Do not calibrate when device tree sets read delay spi: cadence-qspi: Add support for octal DTR flashes mtd: spi-nor-core: Add a ->setup() hook mtd: spi-nor-core: Move SFDP related declarations to top mtd: spi-nor-core: Introduce flash-specific fixup hooks mtd: spi-nor-core: Rework hwcaps selection mtd: spi-nor-core: Add support for DTR protocol mtd: spi-nor-core: Get command opcode extension type from BFPT mtd: spi-nor-core: Parse xSPI Profile 1.0 table mtd: spi-nor-core: Use Read SR dummy cycle and address width from SFDP mtd: spi-nor-core: Enable octal DTR mode when possible mtd: spi-nor-core: Perform a Soft Reset on shutdown mtd: spi-nor-core: Perform a Soft Reset on boot mtd: spi-nor-core: Add support for Cypress Semper flash drivers/mtd/spi/Kconfig | 11 + drivers/mtd/spi/sf_internal.h | 9 + drivers/mtd/spi/sf_probe.c | 9 + drivers/mtd/spi/spi-nor-core.c | 1166 ++++++++++++++++++++++++-------- drivers/mtd/spi/spi-nor-ids.c | 1 + drivers/mtd/spi/spi-nor-tiny.c | 22 - drivers/spi/cadence_qspi.c | 87 ++- drivers/spi/cadence_qspi.h | 15 +- drivers/spi/cadence_qspi_apb.c | 286 +++++++- drivers/spi/spi-mem.c | 3 + include/linux/mtd/spi-nor.h | 261 +++++-- include/spi-mem.h | 16 +- 12 files changed, 1497 insertions(+), 389 deletions(-) --- 2.25.0