Message ID | 20190828104611.3315-1-uboot@andestech.com |
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Headers | show
Return-Path: <u-boot-bounces@lists.denx.de> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46JMzh1p5Fz9sDQ for <incoming@patchwork.ozlabs.org>; Wed, 28 Aug 2019 20:53:36 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E53C3C21F0C; Wed, 28 Aug 2019 10:52:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.4 required=5.0 tests=RDNS_DYNAMIC autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8301EC21C27; Wed, 28 Aug 2019 10:52:35 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AD6CCC21C27; Wed, 28 Aug 2019 10:52:33 +0000 (UTC) Received: from ATCSQR.andestech.com (59-120-53-16.HINET-IP.hinet.net [59.120.53.16]) by lists.denx.de (Postfix) with ESMTPS id 6AE76C21C27 for <u-boot@lists.denx.de>; Wed, 28 Aug 2019 10:52:32 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id x7SAdPV3080775; Wed, 28 Aug 2019 18:39:25 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.15.117) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Wed, 28 Aug 2019 18:52:01 +0800 From: Andes <uboot@andestech.com> To: <u-boot@lists.denx.de> Date: Wed, 28 Aug 2019 18:46:03 +0800 Message-ID: <20190828104611.3315-1-uboot@andestech.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-Originating-IP: [10.0.15.117] X-DNSRBL: X-MAIL: ATCSQR.andestech.com x7SAdPV3080775 Cc: rickchen36@gmail.com, alankao@andestech.com, kclin@andestech.com Subject: [U-Boot] [PATCH v4 0/8] Support Andes RISC-V l2cache on AE350 platform X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
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Support Andes RISC-V l2cache on AE350 platform
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From: Rick Chen <rick@andestech.com> Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse and configure the cache settings (data & instruction prefetch, data & tag latency) from the device tree blob. Also implement L2 cache flush and disable before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Changes in v4: - Remove definitions of v5l2cache.h to cache-v5l2.c Changes in v3: - Add the enable/disable in sandbox_cache.c. - Parse dtb data in v5l2_ofdata_to_platdata() and configure HW in v5l2_probe(). - Move cache_disable() into dcache_disable() of cache.c Changes in v2: - Add new patch [1/7] to support dm cache uclass enable and disable ops. - Use ofdata_to_platdata() to parse and save register base instead of global data. - Rename compatible string of "cache" as "v5l2cache". - make v512_init() return void. - Use dm cache uclass api to disable L2 cache. Rick Chen (8): dm: cache: Add enable and disable ops for cache uclass dm: cache: Add enable and disable ops for sandbox and test dm: cache: add v5l2 cache controller driver riscv: ae350: use the v5l2 driver to configure the cache riscv: ax25: add imply v5l2 cache controller riscv: cache: Flush L2 cache before jump to linux riscv: dts: move out AE350 L2 node from cpus node riscv: cache: use CCTL to flush d-cache arch/riscv/cpu/ax25/Kconfig | 1 + arch/riscv/cpu/ax25/cache.c | 39 +++++-- arch/riscv/dts/ae350_32.dts | 17 +-- arch/riscv/dts/ae350_64.dts | 17 +-- board/AndesTech/ax25-ae350/ax25-ae350.c | 9 ++ drivers/cache/Kconfig | 9 ++ drivers/cache/Makefile | 1 + drivers/cache/cache-uclass.c | 20 ++++ drivers/cache/cache-v5l2.c | 186 ++++++++++++++++++++++++++++++++ drivers/cache/sandbox_cache.c | 13 +++ include/cache.h | 31 ++++++ test/dm/cache.c | 2 + 12 files changed, 324 insertions(+), 21 deletions(-) create mode 100644 drivers/cache/cache-v5l2.c