From patchwork Thu Apr 26 13:38:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 905070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40Wyrc4RRYz9ry1 for ; Thu, 26 Apr 2018 23:41:04 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2B732C220F5; Thu, 26 Apr 2018 13:39:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7DAB9C220E2; Thu, 26 Apr 2018 13:39:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8B52EC2206A; Thu, 26 Apr 2018 13:39:06 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by lists.denx.de (Postfix) with ESMTPS id 28171C21D9A for ; Thu, 26 Apr 2018 13:39:02 +0000 (UTC) Received: from marcel-pc.toradex.int.toradex.int ([46.140.72.82]) by mrelay.perfora.net (mreueus003 [74.208.5.2]) with ESMTPA (Nemesis) id 0MTR0D-1emdAR31tf-00SMIo; Thu, 26 Apr 2018 15:38:45 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Thu, 26 Apr 2018 15:38:36 +0200 Message-Id: <20180426133839.32368-1-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 X-Provags-ID: V03:K1:C08vkZLjKg8I/C8HXS2B1inHVT/H6nlXSaSXs+bHgxcHDa1ucFY AtdKZiuF/z2NnWF7doNvYPveuaCuCI9Y2SfnyTWMBLEPeIyXEOwhxOy97y25Y3ohaY9Wo+o CoYTTg5Xu6Mb4ex2O9N0zoxNxaNhWK78VIIUMYbCoe/VGJChEjzn2j+Vz0lyFGzzPiOaYx0 TLky1ArZyqmNRyusun58g== X-UI-Out-Filterresults: notjunk:1; V01:K0:2VDuRnVpFec=:9F3NQ3m7Hpi+ah6hlD4Ybb ZwCXfO9eztjmzhSN7RjFvAGA/2BAaFx7dQWAN3pyBPW3x9hTaLmiBM7bDALVnL3INNjNxuWzc eKe29qTEJVYzHrvtefxQhOnSkf5l5j/ld49h7aYwS65q8EFNAh+FsYuZz+A6BB+oxja0ub+Dz i8YdBMcTO9Mze4BO3I3qSn8WjtwbisoMy39DQ8PoGJijSavyNoKFt6hYK929o0y+mNdYcozKY 7EAT5Wu8iMbOoCkhhxRKOC/y3dc8cIpQqqc7phFqRTUjhksNqtD7vVcDjVBcRdSODg1m6AK5z V5yAOK1msx+s5McBNwmFNeY9be1EQnmEF8OcUZFFEyE+GD8oRUILpHmLj6E0oBZqvRlDJ4eOv 1Qpp6M2dhJPdJjJ9mTqZcyWQTlU9IyA5fjXLuM9XdLxtPgxQnNY1A62j/9lJBRIGbDcSCxcUE uoohPO3ucXsv0LrgmsKfGmvCXkNzmz/tpDpjDDTVHyAyg+fePhm2QT5BoHOziB6PRcMY9fiF9 gjggjsn2V5HkjMt9ZHsEVqFukxthmqXaMgPVRpIyVUSX0L8HrripNVGvU8XGE7Z87pfqeJYFo M88ab791VDAz8rc2wS6+G2DeuTrLRhbpRYdBXJ6DI/iob5qbZ4zXZeFeZE7jtaNHQGKM8NH0e Jn21lEHHbSJAa5KGKzebySFq0AGvCTAWqAJivzTnfjtRjZmbl+JLIyq9ip/Rol8xQa6o= Cc: Marcel Ziswiler , Marcel Ziswiler , Tom Warren Subject: [U-Boot] [PATCH v3 0/3] fix apalis_t30 optional pcie operation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This series addresses a PCIe reliability issue as observed on Apalis T30 related to a PCIe reset timing violation. This series is available at http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Changes in v3: - Updated copyright period to 2014-2018. - Added a blank line after declarations as warned by patman. - Added Stephen's acked-by. - Rebased and resend as series so far never got applied! Changes in v2: - Leave resp. enable all port 0 pins input drivers as a customer may optionally want to use some of those MXM3 pins as inputs as well. - Stick to struct tegra_pcie_port as suggested by Stephen. - Introduce proper CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT Kconfig option as suggested by Stephen. - Improved the ifdef vs. if curly braces sequencing as suggested by Stephen. - Keep PCIe port reset status in order to safeguard for future changes to the port reset order or even allow for re-initialisation should that ever be implemented in the higher levels of the driver model. Marcel Ziswiler (3): apalis_t30: describe pcie ports apalis_t30: fix pcie port 0 and 1 pin muxing apalis_t30: fix optional pcie port reset for reliable pcie operation arch/arm/dts/tegra30-apalis.dts | 3 ++ board/toradex/apalis_t30/Kconfig | 9 ++++ board/toradex/apalis_t30/apalis_t30.c | 57 +++++++++++++++++++++- .../toradex/apalis_t30/pinmux-config-apalis_t30.h | 16 +++--- 4 files changed, 77 insertions(+), 8 deletions(-)