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Wed, 29 Jul 2020 09:36:25 +0000 From: Sagar Shrikant Kadam To: u-boot@lists.denx.de Cc: rick@andestech.com, paul.walmsley@sifive.com, palmer@dabbelt.com, anup.patel@wdc.com, atish.patra@wdc.com, lukma@denx.de, pragnesh.patel@sifive.com, bin.meng@windriver.com, jagan@amarulasolutions.com, sjg@chromium.org, twoerner@gmail.com, mbrugger@suse.com, Eugeniy.Paltsev@synopsys.com, seanga2@gmail.com, patrick@blueri.se, nsaenzjulienne@suse.de, weijie.gao@mediatek.com, festevam@gmail.com, Sagar Shrikant Kadam Subject: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's Date: Wed, 29 Jul 2020 02:36:09 -0700 Message-Id: <1596015374-25821-1-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: BYAPR07CA0036.namprd07.prod.outlook.com (2603:10b6:a02:bc::49) To BN8PR13MB2611.namprd13.prod.outlook.com (2603:10b6:408:81::17) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from gamma07.internal.sifive.com (64.62.193.194) by BYAPR07CA0036.namprd07.prod.outlook.com (2603:10b6:a02:bc::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3216.23 via Frontend Transport; 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SFTY:; SFS:(6029001)(346002)(366004)(39830400003)(136003)(376002)(396003)(66946007)(6666004)(66476007)(508600001)(66556008)(6916009)(86362001)(36756003)(83380400001)(7416002)(8676002)(186003)(8936002)(956004)(6486002)(26005)(4326008)(52116002)(2616005)(316002)(7696005)(2906002)(16526019)(107886003)(5660300002); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: vQ8jPN7Bgur4mBXI9aSGFT4V/e+OahGCckKjDprl2ibWsrwLcujYgLiz6ekiSwZazr7jAG1t1lANbZtxP9uHn4dnQFfEJy6VZaq2j2Ob8JgXeocL9UdBVLOnImFpICBLYT+zTfRAfIBQOXLAnkd9Ql1tt4mO37uvzlu4p46rvYHtcvDg/i+ryRAkTSunTTSFmiLXJlG9vLVG5cBywYfF/+QYBYkK6rhaD6aaz60Z4asckfaBN6cntR9xLhDkg6SVaYtoi+GJEvEGXoKTVqoomYjY4bitHsWDnmzlnA6XQBTtq8ls6oZrRZej+tPJZWVercYK4ilPuoP3wk1dn63UR2LFdKRAGPgk9VzXL0rwA6oHvRyk9u+VKg5bBsGOjckZGE6YKes2edWt5NbEiJNDv2o6KSmzyqIufgqrlVzsBCWvL59ODR0z8/XPWsJ6kS1gSdSevakuaPZvH29gKaw+3TP8siG2GOocfBiNskcHm10qB+FFXCbt+uvV8t3HWfQoRMD+vILRlqRGpS3b17ItE5QjUdnEBKx87w6d8hmXNjQeEfGKD/APdH320BgnDc6ga3S5MNTnSc8OlR8p3bwDJBtW9HH0eGMgbkjyPhlDJGIZpG/32eisPgdTxiU3pPLAODfemx98Ll1U4lPGD1VY1w== X-OriginatorOrg: sifive.com X-MS-Exchange-CrossTenant-Network-Message-Id: 934bc1d3-6790-48a5-0fc2-08d833a2dcc1 X-MS-Exchange-CrossTenant-AuthSource: BN8PR13MB2611.namprd13.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2020 09:36:25.8661 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 22f88e9d-ae0d-4ed9-b984-cdc9be1529f1 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ncflSl+4r80RoMnq69uGw1j+1BZdM59kKhydx/4gmLCAdrrm/E1AvBFNn3irwPjo5k49j/ZGenLSu3qfKOJGKg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR13MB2611 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The FU540-C000 support in U-Boot is missing DM based reset driver, and is handling reset's to sub-system within the prci driver itself. The series here adds a generic DM reset driver for SiFive SoC's so as to leverage the U-Boot's reset framework and binds the reset driver with prci driver. The PRCI driver takes care of triggering the consumers reset signals appropriately. Patch 1: Add necessary dt indexes for device reset register. Patch 2: Update macro's to use common dt indexes from binding header. Patch 3: Add reset producer and consumer entries within the device tree. Patch 4: Add reset dm driver and bind it within prci module. Patch 5: Add Kconfig, Makefile entries and enable the driver This series is re-based on u-boot-riscv top commit 3b191c56c841 ("Merge branch '2020-07-28-Kconfig-migrations'") History: ========================== V5: -Rebased the series on u-boot-riscv/master. V4: -Rebased the series to u-boot/master. V3: -Add reset indexes in separate dt binding header instead of updating the clock dt binding header which is synced from Linux V2: -Removed extra character in commit log of 2nd patch V1: -Base version. Sagar Shrikant Kadam (5): dt-bindings: prci: add indexes for reset signals available in prci fu540: prci: use common reset indexes defined in binding header fu540: dtsi: add reset producer and consumer entries sifive: reset: add DM based reset driver for SiFive SoC's configs: reset: fu540: enable dm reset framework for SiFive arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 +++ arch/riscv/include/asm/arch-fu540/reset.h | 13 +++ configs/sifive_fu540_defconfig | 2 + drivers/clk/sifive/fu540-prci.c | 90 ++++++++++++++------ drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++ include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++ 8 files changed, 239 insertions(+), 25 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h create mode 100644 drivers/reset/reset-sifive.c create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h