| Message ID | 1504003561-6290-1-git-send-email-tien.fong.chee@intel.com |
|---|---|
| Headers | show
Return-Path: <u-boot-bounces@lists.denx.de> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xhQMX3W32z9t6l for <incoming@patchwork.ozlabs.org>; Tue, 29 Aug 2017 20:47:02 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0E382C21F2D; Tue, 29 Aug 2017 10:46:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4DDF7C21D95; Tue, 29 Aug 2017 10:46:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 30521C21EF7; Tue, 29 Aug 2017 10:46:09 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id E5B30C21DAD for <u-boot@lists.denx.de>; Tue, 29 Aug 2017 10:46:07 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Aug 2017 03:46:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,444,1498546800"; d="scan'208";a="143176539" Received: from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com, ) ([10.226.242.65]) by orsmga005.jf.intel.com with ESMTP; 29 Aug 2017 03:46:03 -0700 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Tue, 29 Aug 2017 18:45:42 +0800 Message-Id: <1504003561-6290-1-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 Cc: Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, Ching Liang See <chin.liang.see@intel.com>, Tien Fong <skywindctf@gmail.com>, Westergteen Dalon <dalon.westergreen@intel.com> Subject: [U-Boot] [PATCH 00/19] Add FPGA, SDRAM drivers and booting to U-boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <https://lists.denx.de/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <https://lists.denx.de/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
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Add FPGA, SDRAM drivers and booting to U-boot
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From: Tien Fong Chee <tien.fong.chee@intel.com> This patchset adding FPGA and SDRAM drivers, enable fpga loadfs and booting to U-boot console. This series is working on top of u-boot.git - http://git.denx.de/u-boot.git Tien Fong Chee (19): configs: Add FPGA loadfs config for Arria 10 configs: Add FAT fs support for SPL arm: socfpga: Add driver for flash to program FPGA arm: socfpga: Add FPGA loadfs command support arm: socfpga: Enhance FPGA program support with at least 4 byte data arm: socfpga: Rename the gen5 sdram driver to more specific name arm: socfpga: Add DRAM bank size initialization function arm: socfpga: Add COMPAT macro for Network on Chip(NoC) arm: socfpga: Add DDR driver for Arria 10 configs: Add DDR Kconfig support for Arria 10 arm: socfpga: Enable build for DDR Arria 10 doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding dts: Add the FPGA design file name to DTS dts: Add device storage and partition to DTS arm: socfpga: Add support to memory allocation in SPL arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 arm: socfpga: Adding clock frequency info for U-boot arm: socfpga: Adding SoCFPGA info for both SPL and U-boot arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 5 +- arch/arm/mach-socfpga/Kconfig | 1 + arch/arm/mach-socfpga/board.c | 21 + arch/arm/mach-socfpga/include/mach/boot0.h | 9 +- .../include/mach/fpga_manager_arria10.h | 27 + arch/arm/mach-socfpga/include/mach/sdram.h | 438 +------------ arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 +++- .../include/mach/{sdram.h => sdram_gen5.h} | 6 +- arch/arm/mach-socfpga/misc_arria10.c | 5 - arch/arm/mach-socfpga/spl.c | 93 +++ cmd/fpga.c | 2 +- common/spl/spl_mmc.c | 2 +- configs/socfpga_arria10_defconfig | 49 ++- disk/part.c | 2 + doc/device-tree-bindings/chosen.txt | 45 ++ drivers/ddr/altera/Kconfig | 2 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_arria10.c | 735 ++++++++++++++++++++ drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0 drivers/fpga/altera.c | 38 +- drivers/fpga/fpga.c | 8 + drivers/fpga/socfpga.c | 14 +- drivers/fpga/socfpga_arria10.c | 386 ++++++++++- include/altera.h | 6 + include/configs/socfpga_common.h | 28 +- include/fdtdec.h | 1 + include/fpga.h | 2 + include/spl.h | 2 + lib/fdtdec.c | 1 + 29 files changed, 1569 insertions(+), 465 deletions(-) copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%) create mode 100644 drivers/ddr/altera/sdram_arria10.c rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)