From patchwork Fri Jun 2 02:04:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Azhar Shaikh X-Patchwork-Id: 770037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wf6w73tXSz9s7p for ; Fri, 2 Jun 2017 12:04:23 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sourceforge.net header.i=@sourceforge.net header.b="Fpoem9b4"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sf.net header.i=@sf.net header.b="XJ0mQK46"; dkim-atps=neutral Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1dGbwm-0000NC-Oe; Fri, 02 Jun 2017 02:04:16 +0000 Received: from sog-mx-2.v43.ch3.sourceforge.com ([172.29.43.192] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1dGbwl-0000N7-SV for tpmdd-devel@lists.sourceforge.net; Fri, 02 Jun 2017 02:04:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sourceforge.net; s=x; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=bv9497r/8Ipd6is1/z7CkbvvP+WN6dK1vdpsCDu3ukE=; b=Fpoem9b4wdo7wofEY/R9jejqusHpeq+5HiRAB8iBLu3bw/bqq3O2EABOJid7+VD9YmFFAorDkYZGfTQ4jN4qhMmG9j/6xdBFv5RxLf3kxnTleRH6PR/3BDxnenQiwM56KaE1uW4EBZJlb2+stW5/U6lY2JOLL8BiGTAPKXmhQ1k=; DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sf.net; s=x; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=bv9497r/8Ipd6is1/z7CkbvvP+WN6dK1vdpsCDu3ukE=; b=XJ0mQK46j+rw+iZimtGFlshKVa9lv4uNIKWThI3b4ne76/YoRyxxt8/7M3+fjPUSI+FM5/9FrVETL0hO2j0QU05P/t3bIgNSvLTFAmWkhDW/nUe98KwDVb2miQCgT68n8iS8rb/3ak4iiF979TfH4/6l2C20UxSbW55AiOGnwxI=; Received-SPF: pass (sog-mx-2.v43.ch3.sourceforge.com: domain of intel.com designates 192.55.52.93 as permitted sender) client-ip=192.55.52.93; envelope-from=azhar.shaikh@intel.com; helo=mga11.intel.com; Received: from mga11.intel.com ([192.55.52.93]) by sog-mx-2.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.76) id 1dGbwh-0007tD-A1 for tpmdd-devel@lists.sourceforge.net; Fri, 02 Jun 2017 02:04:15 +0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Jun 2017 19:04:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,282,1493708400"; d="scan'208";a="94621408" Received: from otc-chromeosbuild-0.jf.intel.com ([10.54.30.57]) by orsmga002.jf.intel.com with ESMTP; 01 Jun 2017 19:04:04 -0700 From: Azhar Shaikh To: jarkko.sakkinen@linux.intel.com, jgunthorpe@obsidianresearch.com, tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org Date: Thu, 1 Jun 2017 19:04:04 -0700 Message-Id: <1496369044-38234-1-git-send-email-azhar.shaikh@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496344432-76640-1-git-send-email-azhar.shaikh@intel.com> References: <1496344432-76640-1-git-send-email-azhar.shaikh@intel.com> X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain X-Headers-End: 1dGbwh-0007tD-A1 Subject: [tpmdd-devel] [PATCH v2] tpm: Enable CLKRUN protocol for Braswell systems X-BeenThere: tpmdd-devel@lists.sourceforge.net X-Mailman-Version: 2.1.21 Precedence: list List-Id: Tpm Device Driver maintainance List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-security-module@vger.kernel.org, azhar.shaikh@intel.com MIME-Version: 1.0 Errors-To: tpmdd-devel-bounces@lists.sourceforge.net To overcome a hardware limitation on Intel Braswell systems, disable CLKRUN protocol during TPM transactions and re-enable once the transaction is completed. Signed-off-by: Azhar Shaikh --- Changes from v1: - Add CONFIG_X86 around disable_lpc_clk_run () and enable_lpc_clk_run() to avoid - build breakage on architectures which do not implement kmap_atomic_pfn() drivers/char/tpm/tpm.h | 20 ++++++++++ drivers/char/tpm/tpm_tis.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index 4b4c8dee3096..98032a22317e 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h @@ -36,6 +36,10 @@ #include #include +#ifdef CONFIG_X86 +#include +#endif + enum tpm_const { TPM_MINOR = 224, /* officially assigned */ TPM_BUFSIZE = 4096, @@ -436,6 +440,22 @@ struct tpm_buf { u8 *data; }; +#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000 +#define LPC_CNTRL_REG_OFFSET 0x84 +#define LPC_CLKRUN_EN (1 << 2) + +#ifdef CONFIG_X86 +static inline bool is_bsw(void) +{ + return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0); +} +#else +static inline bool is_bsw(void) +{ + return false; +} +#endif + static inline int tpm_buf_init(struct tpm_buf *buf, u16 tag, u32 ordinal) { struct tpm_input_header *head; diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c index c7e1384f1b08..0c1496340a18 100644 --- a/drivers/char/tpm/tpm_tis.c +++ b/drivers/char/tpm/tpm_tis.c @@ -89,13 +89,79 @@ static inline int is_itpm(struct acpi_device *dev) } #endif +#ifdef CONFIG_X86 +/** + * disable_lpc_clk_run() - clear LPC CLKRUN_EN i.e. clocks will be free running + */ +static void disable_lpc_clk_run(void) +{ + u32 clkrun_val; + void __iomem *ilb_base_addr = NULL; + + ilb_base_addr = (void __iomem *) + kmap_atomic_pfn(INTEL_LEGACY_BLK_BASE_ADDR >> PAGE_SHIFT); + + clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + /* Disable LPC CLKRUN# */ + clkrun_val &= ~LPC_CLKRUN_EN; + iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + kunmap_atomic(ilb_base_addr); + /* + * Write any random value on port 0x80 which is on LPC, to make + * sure LPC clock is running before sending any TPM command. + */ + outb(0x80, 0xCC); +} + +/** + * enable_lpc_clk_run() - set LPC CLKRUN_EN i.e. clocks can be turned off + */ +static void enable_lpc_clk_run(void) +{ + u32 clkrun_val; + void __iomem *ilb_base_addr = NULL; + + ilb_base_addr = (void __iomem *) + kmap_atomic_pfn(INTEL_LEGACY_BLK_BASE_ADDR >> PAGE_SHIFT); + + clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + /* Enable LPC CLKRUN# */ + clkrun_val |= LPC_CLKRUN_EN; + iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + kunmap_atomic(ilb_base_addr); + /* + * Write any random value on port 0x80 which is on LPC, to make + * sure LPC clock is running before sending any TPM command. + */ + outb(0x80, 0xCC); +} +#else +static void disable_lpc_clk_run(void) +{ +} +static void enable_lpc_clk_run(void) +{ +} +#endif + static int tpm_tcg_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len, u8 *result) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + if (is_bsw()) + disable_lpc_clk_run(); + while (len--) *result++ = ioread8(phy->iobase + addr); + + if (is_bsw()) + enable_lpc_clk_run(); + return 0; } @@ -104,8 +170,15 @@ static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len, { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + if (is_bsw()) + disable_lpc_clk_run(); + while (len--) iowrite8(*value++, phy->iobase + addr); + + if (is_bsw()) + enable_lpc_clk_run(); + return 0; } @@ -113,7 +186,14 @@ static int tpm_tcg_read16(struct tpm_tis_data *data, u32 addr, u16 *result) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + if (is_bsw()) + disable_lpc_clk_run(); + *result = ioread16(phy->iobase + addr); + + if (is_bsw()) + enable_lpc_clk_run(); + return 0; } @@ -121,7 +201,14 @@ static int tpm_tcg_read32(struct tpm_tis_data *data, u32 addr, u32 *result) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + if (is_bsw()) + disable_lpc_clk_run(); + *result = ioread32(phy->iobase + addr); + + if (is_bsw()) + enable_lpc_clk_run(); + return 0; } @@ -129,7 +216,14 @@ static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + if (is_bsw()) + disable_lpc_clk_run(); + iowrite32(value, phy->iobase + addr); + + if (is_bsw()) + enable_lpc_clk_run(); + return 0; }