From patchwork Tue Jul 18 15:30:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 790344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xBkd05MQZz9s7C for ; Wed, 19 Jul 2017 01:30:28 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xBkd01ZSbzDrHD for ; Wed, 19 Jul 2017 01:30:28 +1000 (AEST) X-Original-To: slof@lists.ozlabs.org Delivered-To: slof@lists.ozlabs.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xBkcw2GYWzDrH1 for ; Wed, 19 Jul 2017 01:30:23 +1000 (AEST) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7DD8E4A710; Tue, 18 Jul 2017 15:30:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7DD8E4A710 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=thuth@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 7DD8E4A710 Received: from thh440s.str.redhat.com (dhcp-200-180.str.redhat.com [10.33.200.180]) by smtp.corp.redhat.com (Postfix) with ESMTP id D5DDF6292E; Tue, 18 Jul 2017 15:30:20 +0000 (UTC) From: Thomas Huth To: slof@lists.ozlabs.org Date: Tue, 18 Jul 2017 17:30:20 +0200 Message-Id: <1500391820-28680-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 18 Jul 2017 15:30:21 +0000 (UTC) Subject: [SLOF] [PATCH] pci-scan: Fix pci-bridge-set-mem-base and pci-bridge-set-mem-limit X-BeenThere: slof@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "Patches for https://github.com/aik/SLOF" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: slof-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "SLOF" The functions used a bogus mixture between programming the registers with pci-next-mem64 and pci-next-mem - the upper register bits were filled with the value from the 64-bit memory space while the lower bits were filled with the bits from the 32-bit memory space variable. Signed-off-by: Thomas Huth Reviewed-by: Nikunj A Dadhania --- slof/fs/pci-scan.fs | 83 +++++++++++++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 37 deletions(-) diff --git a/slof/fs/pci-scan.fs b/slof/fs/pci-scan.fs index c39707a..a97afa3 100644 --- a/slof/fs/pci-scan.fs +++ b/slof/fs/pci-scan.fs @@ -104,47 +104,56 @@ here 100 allot CONSTANT pci-device-vec or swap 20 + rtas-config-l! \ and write it into the Reg ; -\ Update pci-next-mem to be 1MB aligned and set the mem-base and mem-base-upper register -\ and set the Limit register to the maximum available address space -\ needed for scanning possible devices behind the bridge +\ Update pci-next-mem (or mem64) to be aligned and set the mem-base and +\ mem-base-upper register. Also set the Limit register to the maximum available +\ address space needed for scanning possible devices behind the bridge : pci-bridge-set-mem-base ( addr -- ) - pci-next-mem @ 100000 #aligned \ read the current Value and align to 1MB boundary - dup pci-next-mem ! \ and write it back - over 24 + rtas-config-w@ \ check if 64bit support - 1 and IF \ IF 64 bit support - pci-next-mem64 @ 100000000 #aligned \ | read the current Value of 64-bit and align to 4GB boundary - dup 100000000 + pci-next-mem64 x! \ | and write back with 1GB for bridge - 2 pick swap \ | - 20 rshift \ | keep upper 32 bits - swap 28 + rtas-config-l! \ | and write it into the Base-Upper32-bits - pci-max-mem64 @ 20 rshift \ | fetch max Limit address and keep upper 32 bits - 2 pick 2C + rtas-config-l! \ | and set the Limit - THEN \ FI - 10 rshift \ keep upper 16 bits - pci-max-mem @ 1- FFFF0000 and or \ and Insert mmem Limit (set it to max) - swap 24 + rtas-config-l! \ and write it into the bridge + dup 24 + rtas-config-w@ 1 and \ does bridge support 64-bit? + pci-next-mem64 @ 0<> and IF \ and do we have 64-bit memory? + \ Align variable to 4GB boundary + pci-next-mem64 @ 100000000 #aligned + dup pci-next-mem64 x! + \ Set base and limit registers: + 20 rshift over 28 + rtas-config-l! \ set prefetch base upper 32 bits + pci-next-mem64 @ 10 rshift FFF0 and + pci-max-mem64 @ 1- FFF00000 and or + over 24 + rtas-config-l! \ set prefetch limit & base lower + pci-max-mem64 @ 1- 20 rshift + swap 2C + rtas-config-l! \ and set the limit upper 32 bits + ELSE + \ Align variable to 1MB boundary + pci-next-mem @ 100000 #aligned + dup pci-next-mem ! + \ Set base and limit register: + 10 rshift FFF0 and + pci-max-mem @ 1- FFF00000 and or + swap 24 + rtas-config-l! + THEN ; -\ Update pci-next-mem to be 1MB aligned and set the mem-limit register -\ The Limit Value is one less then the upper boundary -\ If the limit is less than the base the mem is disabled +\ Update pci-next-mem (or -mem64) to be aligned (with some additional space +\ for hot-plugging later) and set the mem-limit register. The Limit Value is +\ one less then the upper boundary. : pci-bridge-set-mem-limit ( addr -- ) - pci-next-mem @ 100000 + \ add space for hot-plugging - 100000 #aligned \ align to 1MB boundary - dup pci-next-mem ! \ and write it back - 1- \ make limit one less than boundary - over 24 + rtas-config-w@ \ check if 64bit support - 1 and IF \ IF 64 bit support - pci-next-mem64 @ 100000000 #aligned \ | Reat current value of 64-bar and align at 4GB - dup pci-next-mem64 x! \ | and write it back - 1- \ | make limite one less than boundary - 2 pick swap \ | - 20 rshift \ | keep upper 32 bits - swap 2C + rtas-config-l! \ | and write it into the Limit-Upper32-bits - THEN \ FI - FFFF0000 and \ keep upper 16 bits - over 24 + rtas-config-l@ 0000FFFF and \ fetch original Value - or swap 24 + rtas-config-l! \ and write it into the bridge + dup 24 + rtas-config-w@ 1 and \ does bridge support 64-bit? + pci-next-mem64 @ 0<> and IF \ and do we have 64-bit memory? + \ Update current variable (add space for hot-plugging and align it) + pci-next-mem64 @ 80000000 + + 100000000 #aligned + dup pci-next-mem64 x! + \ Update the limit registers: + 1- 20 rshift + over 2C + rtas-config-l! \ set the limit upper 32 bits + pci-next-mem64 @ 1- 10 rshift + swap 26 + rtas-config-w! \ set limit lower bits + ELSE + \ Update current variable (add space for hot-plugging and align it) + pci-next-mem @ 100000 + + 100000 #aligned + dup pci-next-mem ! + 1- 10 rshift + swap 26 + rtas-config-w! + THEN ; \ Update pci-next-io to be 4KB aligned and set the io-base and io-base-upper register