| Message ID | 8e7850ca3aa8928a3e93164ed5a3147cbd79afe5.1544597914.git-series.andrew.donnellan@au1.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support OpenCAPI and NVLink devices on same NPU on Witherspoon | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | master/apply_patch Successfully applied |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | success | Test snowpatch/job/snowpatch-skiboot on branch master |
Le 12/12/2018 à 07:58, Andrew Donnellan a écrit : > Now that we've moved most of the BAR assignment code into common code and > we have an existing struct npu2 everywhere we need it, we don't need the > gcid and scom parameters to npu2_write_bar() any more. > > Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > --- That one feels good! Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> > hw/npu2-common.c | 14 +++++--------- > hw/npu2-opencapi.c | 4 ++-- > hw/npu2.c | 6 +++--- > include/npu2.h | 3 +-- > 4 files changed, 11 insertions(+), 16 deletions(-) > > diff --git a/hw/npu2-common.c b/hw/npu2-common.c > index b140e9ffd064..6cbae9bffaf9 100644 > --- a/hw/npu2-common.c > +++ b/hw/npu2-common.c > @@ -141,8 +141,7 @@ void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar) > } > } > > -void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, > - uint32_t scom) > +void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar) > { > uint64_t reg, val; > int block; > @@ -168,10 +167,7 @@ void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, > > for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) { > reg = NPU2_REG_OFFSET(0, block, bar->reg); > - if (p) > - npu2_write(p, reg, val); > - else > - npu2_scom_write(gcid, scom, reg, NPU2_MISC_DA_LEN_8B, val); > + npu2_write(p, reg, val); > } > } > > @@ -200,7 +196,7 @@ static void assign_bars(struct npu2 *npu) > for (i = 0; i < ARRAY_SIZE(phy_bars); i++) { > bar = &phy_bars[i]; > npu2_get_bar(npu->chip_id, bar); > - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); > + npu2_write_bar(npu, bar); > } > > /* Device BARs */ > @@ -221,7 +217,7 @@ static void assign_bars(struct npu2 *npu) > NPU2_NTL0_BAR : NPU2_NTL1_BAR); > bar->flags = PCI_CFG_BAR_TYPE_MEM | PCI_CFG_BAR_MEM64; > npu2_get_bar(npu->chip_id, bar); > - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); > + npu2_write_bar(npu, bar); > > /* GENID BAR */ > bar = &dev->genid_bar; > @@ -234,7 +230,7 @@ static void assign_bars(struct npu2 *npu) > bar->size = 0x10000; > if (NPU2DEV_BRICK(dev)) > bar->base += 0x10000; > - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); > + npu2_write_bar(npu, bar); > }; > > /* Global MMIO BAR */ > diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c > index b374a1035ac9..cc7c403351ce 100644 > --- a/hw/npu2-opencapi.c > +++ b/hw/npu2-opencapi.c > @@ -742,7 +742,7 @@ static void setup_afu_mmio_bars(uint32_t gcid, uint32_t scom_base, > > prlog(PR_DEBUG, "OCAPI: %s: Setup AFU MMIO BARs\n", __func__); > dev->ntl_bar.enabled = true; > - npu2_write_bar(dev->npu, &dev->ntl_bar, gcid, scom_base); > + npu2_write_bar(dev->npu, &dev->ntl_bar); > > reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_ADDR, 0ull, dev->ntl_bar.base >> 16); > reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_SIZE, reg, ilog2(dev->ntl_bar.size >> 16)); > @@ -1578,7 +1578,7 @@ static void setup_device(struct npu2_dev *dev) > setup_afu_mmio_bars(dev->npu->chip_id, dev->npu->xscom_base, dev); > /* Procedure 13.1.3.9 - AFU Config BARs */ > dev->genid_bar.enabled = true; > - npu2_write_bar(dev->npu, &dev->genid_bar, dev->npu->chip_id, dev->npu->xscom_base); > + npu2_write_bar(dev->npu, &dev->genid_bar); > > set_fence_control(dev->npu->chip_id, dev->npu->xscom_base, dev->brick_index, 0b00); > > diff --git a/hw/npu2.c b/hw/npu2.c > index 6aa16a43f803..1e9fb581688f 100644 > --- a/hw/npu2.c > +++ b/hw/npu2.c > @@ -131,7 +131,7 @@ static int64_t npu2_cfg_write_cmd(void *dev, > enabled = !!(*data & PCI_CFG_CMD_MEM_EN); > > ndev->ntl_bar.enabled = enabled; > - npu2_write_bar(ndev->npu, &ndev->ntl_bar, 0, 0); > + npu2_write_bar(ndev->npu, &ndev->ntl_bar); > > /* > * Enable/disable the GENID BAR. Two bricks share one GENID > @@ -146,7 +146,7 @@ static int64_t npu2_cfg_write_cmd(void *dev, > /* Enable the BAR if either device requests it enabled, otherwise disable it */ > ndev->genid_bar.enabled = ndev->genid_bar.enabled0 || > ndev->genid_bar.enabled1; > - npu2_write_bar(ndev->npu, &ndev->genid_bar, 0, 0); > + npu2_write_bar(ndev->npu, &ndev->genid_bar); > > return OPAL_PARTIAL; > } > @@ -220,7 +220,7 @@ static int64_t npu2_cfg_write_bar(struct npu2_dev *dev, > return OPAL_HARDWARE; > } > > - npu2_write_bar(dev->npu, bar, 0, 0); > + npu2_write_bar(dev->npu, bar); > } > > /* To update the config cache */ > diff --git a/include/npu2.h b/include/npu2.h > index bf7fb6927dd4..64be9f4eb9dd 100644 > --- a/include/npu2.h > +++ b/include/npu2.h > @@ -214,8 +214,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); > void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask); > void npu2_get_bar(uint32_t gcid, struct npu2_bar *bar); > void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar); > -void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, > - uint32_t scom); > +void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar); > int64_t npu2_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, > uint32_t offset, uint32_t len, uint32_t *data, > bool write); >
diff --git a/hw/npu2-common.c b/hw/npu2-common.c index b140e9ffd064..6cbae9bffaf9 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -141,8 +141,7 @@ void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar) } } -void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, - uint32_t scom) +void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar) { uint64_t reg, val; int block; @@ -168,10 +167,7 @@ void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, for (block = NPU2_BLOCK_SM_0; block <= NPU2_BLOCK_SM_3; block++) { reg = NPU2_REG_OFFSET(0, block, bar->reg); - if (p) - npu2_write(p, reg, val); - else - npu2_scom_write(gcid, scom, reg, NPU2_MISC_DA_LEN_8B, val); + npu2_write(p, reg, val); } } @@ -200,7 +196,7 @@ static void assign_bars(struct npu2 *npu) for (i = 0; i < ARRAY_SIZE(phy_bars); i++) { bar = &phy_bars[i]; npu2_get_bar(npu->chip_id, bar); - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); + npu2_write_bar(npu, bar); } /* Device BARs */ @@ -221,7 +217,7 @@ static void assign_bars(struct npu2 *npu) NPU2_NTL0_BAR : NPU2_NTL1_BAR); bar->flags = PCI_CFG_BAR_TYPE_MEM | PCI_CFG_BAR_MEM64; npu2_get_bar(npu->chip_id, bar); - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); + npu2_write_bar(npu, bar); /* GENID BAR */ bar = &dev->genid_bar; @@ -234,7 +230,7 @@ static void assign_bars(struct npu2 *npu) bar->size = 0x10000; if (NPU2DEV_BRICK(dev)) bar->base += 0x10000; - npu2_write_bar(npu, bar, npu->chip_id, npu->xscom_base); + npu2_write_bar(npu, bar); }; /* Global MMIO BAR */ diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index b374a1035ac9..cc7c403351ce 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -742,7 +742,7 @@ static void setup_afu_mmio_bars(uint32_t gcid, uint32_t scom_base, prlog(PR_DEBUG, "OCAPI: %s: Setup AFU MMIO BARs\n", __func__); dev->ntl_bar.enabled = true; - npu2_write_bar(dev->npu, &dev->ntl_bar, gcid, scom_base); + npu2_write_bar(dev->npu, &dev->ntl_bar); reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_ADDR, 0ull, dev->ntl_bar.base >> 16); reg = SETFIELD(NPU2_CQ_CTL_MISC_MMIOPA_SIZE, reg, ilog2(dev->ntl_bar.size >> 16)); @@ -1578,7 +1578,7 @@ static void setup_device(struct npu2_dev *dev) setup_afu_mmio_bars(dev->npu->chip_id, dev->npu->xscom_base, dev); /* Procedure 13.1.3.9 - AFU Config BARs */ dev->genid_bar.enabled = true; - npu2_write_bar(dev->npu, &dev->genid_bar, dev->npu->chip_id, dev->npu->xscom_base); + npu2_write_bar(dev->npu, &dev->genid_bar); set_fence_control(dev->npu->chip_id, dev->npu->xscom_base, dev->brick_index, 0b00); diff --git a/hw/npu2.c b/hw/npu2.c index 6aa16a43f803..1e9fb581688f 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -131,7 +131,7 @@ static int64_t npu2_cfg_write_cmd(void *dev, enabled = !!(*data & PCI_CFG_CMD_MEM_EN); ndev->ntl_bar.enabled = enabled; - npu2_write_bar(ndev->npu, &ndev->ntl_bar, 0, 0); + npu2_write_bar(ndev->npu, &ndev->ntl_bar); /* * Enable/disable the GENID BAR. Two bricks share one GENID @@ -146,7 +146,7 @@ static int64_t npu2_cfg_write_cmd(void *dev, /* Enable the BAR if either device requests it enabled, otherwise disable it */ ndev->genid_bar.enabled = ndev->genid_bar.enabled0 || ndev->genid_bar.enabled1; - npu2_write_bar(ndev->npu, &ndev->genid_bar, 0, 0); + npu2_write_bar(ndev->npu, &ndev->genid_bar); return OPAL_PARTIAL; } @@ -220,7 +220,7 @@ static int64_t npu2_cfg_write_bar(struct npu2_dev *dev, return OPAL_HARDWARE; } - npu2_write_bar(dev->npu, bar, 0, 0); + npu2_write_bar(dev->npu, bar); } /* To update the config cache */ diff --git a/include/npu2.h b/include/npu2.h index bf7fb6927dd4..64be9f4eb9dd 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -214,8 +214,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask); void npu2_get_bar(uint32_t gcid, struct npu2_bar *bar); void npu2_read_bar(struct npu2 *p, struct npu2_bar *bar); -void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar, uint32_t gcid, - uint32_t scom); +void npu2_write_bar(struct npu2 *p, struct npu2_bar *bar); int64_t npu2_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write);
Now that we've moved most of the BAR assignment code into common code and we have an existing struct npu2 everywhere we need it, we don't need the gcid and scom parameters to npu2_write_bar() any more. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> --- hw/npu2-common.c | 14 +++++--------- hw/npu2-opencapi.c | 4 ++-- hw/npu2.c | 6 +++--- include/npu2.h | 3 +-- 4 files changed, 11 insertions(+), 16 deletions(-)