From patchwork Wed Dec 12 06:58:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Donnellan X-Patchwork-Id: 1011602 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43F7674xpNz9s47 for ; Wed, 12 Dec 2018 18:02:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43F7671DQ2zDqwD for ; Wed, 12 Dec 2018 18:02:07 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=au1.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=andrew.donnellan@au1.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=au1.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43F73D5cJ7zDql9 for ; Wed, 12 Dec 2018 17:59:36 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wBC6wRVI009894 for ; Wed, 12 Dec 2018 01:59:35 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2pauvebq99-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 12 Dec 2018 01:59:34 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 12 Dec 2018 06:59:29 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wBC6xSOA57868508 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Dec 2018 06:59:28 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6CAD0A4065; Wed, 12 Dec 2018 06:59:28 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C950DA405C; Wed, 12 Dec 2018 06:59:27 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 12 Dec 2018 06:59:27 +0000 (GMT) Received: from intelligence.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher DHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id 09636A039A; Wed, 12 Dec 2018 17:59:25 +1100 (AEDT) From: Andrew Donnellan To: skiboot@lists.ozlabs.org Date: Wed, 12 Dec 2018 17:58:54 +1100 X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: X-TM-AS-GCONF: 00 x-cbid: 18121206-4275-0000-0000-000002EF53CA X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18121206-4276-0000-0000-000037FC7451 Message-Id: <87ffa1801b51c2f13e39128c57b50596be50215d.1544597914.git-series.andrew.donnellan@au1.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-12-12_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812120061 Subject: [Skiboot] [PATCH 11/13] hw/npu2: Fix OpenCAPI PE assignment X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au, arbab@linux.ibm.com, fbarrat@linux.vnet.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When we support mixing NVLink and OpenCAPI devices on the same NPU, we're going to have to share the same range of 16 PE numbers between NVLink and OpenCAPI PHBs. For OpenCAPI devices, PE assignment is only significant for determining which System Interrupt Log register is used for a particular brick - unlike NVLink, it doesn't play any role in determining how links are fenced. Split the PE range into a lower half which is used for NVLink, and an upper half that is used for OpenCAPI, with a fixed PE number assigned per brick. As the PE assignment for OpenCAPI devices is fixed, set the PE once during device init and then ignore calls to the set_pe() operation. Suggested-by: Frederic Barrat Signed-off-by: Andrew Donnellan --- hw/npu2-opencapi.c | 75 +++++++++++++++++++++-------------------------- include/npu2.h | 21 +++++++++++-- 2 files changed, 52 insertions(+), 44 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index d79727ad4199..a57f556b102d 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -482,6 +482,20 @@ static void brick_config(uint32_t gcid, uint32_t scom_base, int index) enable_pb_snooping(gcid, scom_base, index); } +/* Procedure 13.1.3.4 - Brick to PE Mapping */ +static void pe_config(struct npu2_dev *dev) +{ + /* We currently use a fixed PE assignment per brick */ + uint64_t val, reg; + val = NPU2_MISC_BRICK_BDF2PE_MAP_ENABLE; + val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_PE, val, NPU2_OCAPI_PE(dev)); + val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_BDF, val, 0); + reg = NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, + NPU2_MISC_BRICK0_BDF2PE_MAP0 + + (dev->brick_index * 0x18)); + npu2_write(dev->npu, reg, val); +} + /* Procedure 13.1.3.5 - TL Configuration */ static void tl_config(uint32_t gcid, uint32_t scom_base, uint64_t index) { @@ -1214,48 +1228,18 @@ static int64_t npu2_opencapi_ioda_reset(struct phb __unused *phb, return OPAL_SUCCESS; } -static int64_t npu2_opencapi_set_pe(struct phb *phb, - uint64_t pe_num, - uint64_t bdfn, - uint8_t bcompare, - uint8_t dcompare, - uint8_t fcompare, - uint8_t action) +static int64_t npu2_opencapi_set_pe(struct phb __unused *phb, + uint64_t __unused pe_num, + uint64_t __unused bdfn, + uint8_t __unused bcompare, + uint8_t __unused dcompare, + uint8_t __unused fcompare, + uint8_t __unused action) { - struct npu2 *p; - struct npu2_dev *dev; - uint64_t reg, val, pe_bdfn; - - /* Sanity check */ - if (action != OPAL_MAP_PE && action != OPAL_UNMAP_PE) - return OPAL_PARAMETER; - if (pe_num >= NPU2_MAX_PE_NUM) - return OPAL_PARAMETER; - if (bdfn >> 8) - return OPAL_PARAMETER; - if (bcompare != OpalPciBusAll || - dcompare != OPAL_COMPARE_RID_DEVICE_NUMBER || - fcompare != OPAL_COMPARE_RID_FUNCTION_NUMBER) - return OPAL_UNSUPPORTED; - - /* Get the NPU2 device */ - dev = phb_to_npu2_dev_ocapi(phb); - if (!dev) - return OPAL_PARAMETER; - - p = dev->npu; - - pe_bdfn = dev->bdfn; - - val = NPU2_MISC_BRICK_BDF2PE_MAP_ENABLE; - val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_PE, val, pe_num); - val = SETFIELD(NPU2_MISC_BRICK_BDF2PE_MAP_BDF, val, pe_bdfn); - reg = NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_MISC, - NPU2_MISC_BRICK0_BDF2PE_MAP0 + - (dev->brick_index * 0x18)); - p->bdf2pe_cache[dev->brick_index] = val; - npu2_write(p, reg, val); - + /* + * Ignored on OpenCAPI - we use fixed PE assignments. May need + * addressing when we support dual-link devices. + */ return OPAL_SUCCESS; } @@ -1424,7 +1408,13 @@ static void setup_device(struct npu2_dev *dev) dt_add_property_cells(dn_phb, "ibm,links", 1); dt_add_property(dn_phb, "ibm,mmio-window", mm_win, sizeof(mm_win)); dt_add_property_cells(dn_phb, "ibm,phb-diag-data-size", 0); + + /* + * We ignore whatever PE numbers Linux tries to set, so we just + * advertise enough that Linux won't complain + */ dt_add_property_cells(dn_phb, "ibm,opal-num-pes", NPU2_MAX_PE_NUM); + dt_add_property_cells(dn_phb, "ibm,opal-reserved-pe", NPU2_RESERVED_PE_NUM); dt_add_property_cells(dn_phb, "ranges", 0x02000000, hi32(mm_win[0]), lo32(mm_win[0]), @@ -1504,6 +1494,9 @@ int npu2_opencapi_init_npu(struct npu2 *npu) /* Procedure 13.1.3.1 - Select OCAPI vs NVLink */ brick_config(npu->chip_id, npu->xscom_base, dev->brick_index); + /* Procedure 13.1.3.4 - Brick to PE Mapping */ + pe_config(dev); + /* Procedure 13.1.3.5 - Transaction Layer Configuration */ tl_config(npu->chip_id, npu->xscom_base, dev->brick_index); diff --git a/include/npu2.h b/include/npu2.h index 8f4747006980..c7b20f19fde1 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -45,9 +45,24 @@ dev->npu->chip_id, dev->brick_index, ## a) -/* Number of PEs supported */ -#define NPU2_MAX_PE_NUM 16 -#define NPU2_RESERVED_PE_NUM 15 +/* + * Number of PEs supported + * + * The NPU supports PE numbers from 0-15. At present, we only assign a maximum + * of 1 PE per brick. + * + * NVLink devices are currently exposed to Linux underneath a single virtual + * PHB. Therefore, we give NVLink half the available PEs, which is enough for + * 6 bricks plus 1 reserved PE. + * + * For OpenCAPI, the BDF-to-PE registers are used exclusively for mapping + * bricks to System Interrupt Log registers (the BDF component of those + * registers is ignored). Currently, we allocate a fixed PE based on the brick + * index in the upper half of the PE namespace. + */ +#define NPU2_MAX_PE_NUM 8 +#define NPU2_RESERVED_PE_NUM 7 +#define NPU2_OCAPI_PE(ndev) ((ndev)->brick_index + NPU2_MAX_PE_NUM) #define NPU2_LINKS_PER_CHIP 6