Message ID | 20210804072137.1147875-46-hegdevasant@linux.vnet.ibm.com |
---|---|
State | Accepted |
Headers | show
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Wed, 4 Aug 2021 07:23:19 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.83.73]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 4 Aug 2021 07:23:18 +0000 (GMT) From: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> To: skiboot@lists.ozlabs.org Date: Wed, 4 Aug 2021 12:51:23 +0530 Message-Id: <20210804072137.1147875-46-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> References: <20210804072137.1147875-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: VyZGnSn-dRStB42Qj9UZ28GX-bk-81kH X-Proofpoint-GUID: VyZGnSn-dRStB42Qj9UZ28GX-bk-81kH X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-04_02:2021-08-03, 2021-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=665 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108040036 Subject: [Skiboot] [PATCH v2 45/59] xive/p10: Activate has_array when PQ_disable is available X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development <skiboot.lists.ozlabs.org> List-Unsubscribe: <https://lists.ozlabs.org/options/skiboot>, <mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe> List-Archive: <http://lists.ozlabs.org/pipermail/skiboot/> List-Post: <mailto:skiboot@lists.ozlabs.org> List-Help: <mailto:skiboot-request@lists.ozlabs.org?subject=help> List-Subscribe: <https://lists.ozlabs.org/listinfo/skiboot>, <mailto:skiboot-request@lists.ozlabs.org?subject=subscribe> Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" <skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org> |
Series |
P10 Enablement
|
expand
|
diff --git a/hw/xive2.c b/hw/xive2.c index 0f9c93d6a..1ad1f138d 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -1610,15 +1610,20 @@ static bool xive_cfg_save_restore(struct xive *x) * 1/3rd of the cache is reserved for PHB ESBs and the rest to * IPIs. This is sufficient to keep all the PHB ESBs in cache and * avoid ESB cache misses during IO interrupt processing. + * + * hash_array_enable : + * Internal cache hashing optimization. The hash_array tracks for + * ESBs where the original trigger came from so that we avoid + * getting the EAS into the cache twice. */ static void xive_config_esb_cache(struct xive *x) { uint64_t val = xive_regr(x, VC_ESBC_CFG); if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) { - val |= VC_ESBC_CFG_SPLIT_MODE; - xive_dbg(x, "ESB cache configured with split mode. " - "VC_ESBC_CFG=%016llx\n", val); + val |= VC_ESBC_CFG_SPLIT_MODE | VC_ESBC_CFG_HASH_ARRAY_ENABLE; + xive_dbg(x, "ESB cache configured with split mode " + "and hash array. VC_ESBC_CFG=%016llx\n", val); } else val &= ~VC_ESBC_CFG_SPLIT_MODE; diff --git a/include/xive2-regs.h b/include/xive2-regs.h index 4638c3d89..c2ed265f6 100644 --- a/include/xive2-regs.h +++ b/include/xive2-regs.h @@ -230,6 +230,8 @@ /* ESBC configuration */ #define X_VC_ESBC_CFG 0x148 #define VC_ESBC_CFG 0x240 +#define VC_ESBC_CFG_HASH_ARRAY_ENABLE PPC_BIT(40) +#define VC_ESBC_CFG_HASH_STORE_MODE PPC_BITMASK(41,42) #define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56) /* EASC flush control register */