@@ -1602,6 +1602,29 @@ static bool xive_cfg_save_restore(struct xive *x)
return !!(x->config & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE);
}
+/*
+ * When PQ_disable is available, configure the ESB cache to improve
+ * performance for PHB ESBs.
+ *
+ * split_mode :
+ * 1/3rd of the cache is reserved for PHB ESBs and the rest to
+ * IPIs. This is sufficient to keep all the PHB ESBs in cache and
+ * avoid ESB cache misses during IO interrupt processing.
+ */
+static void xive_config_esb_cache(struct xive *x)
+{
+ uint64_t val = xive_regr(x, VC_ESBC_CFG);
+
+ if (xive_has_cap(x, CQ_XIVE_CAP_PHB_PQ_DISABLE)) {
+ val |= VC_ESBC_CFG_SPLIT_MODE;
+ xive_dbg(x, "ESB cache configured with split mode. "
+ "VC_ESBC_CFG=%016llx\n", val);
+ } else
+ val &= ~VC_ESBC_CFG_SPLIT_MODE;
+
+ xive_regw(x, VC_ESBC_CFG, val);
+}
+
static void xive_config_fused_core(struct xive *x)
{
uint64_t val = xive_regr(x, TCTXT_CFG);
@@ -1717,6 +1740,8 @@ static bool xive_config_init(struct xive *x)
xive_config_fused_core(x);
+ xive_config_esb_cache(x);
+
xive_config_reduced_priorities_fixup(x);
return true;
@@ -227,6 +227,11 @@
#define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32,35)
#define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36,63) /* 28-bit */
+/* ESBC configuration */
+#define X_VC_ESBC_CFG 0x148
+#define VC_ESBC_CFG 0x240
+#define VC_ESBC_CFG_SPLIT_MODE PPC_BIT(56)
+
/* EASC flush control register */
#define X_VC_EASC_FLUSH_CTRL 0x160
#define VC_EASC_FLUSH_CTRL 0x300