From patchwork Mon Jul 19 13:20:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasant Hegde X-Patchwork-Id: 1507072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=jM5jKJQz; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GT2dy4CzWz9sWl for ; Mon, 19 Jul 2021 23:25:26 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4GT2dy393Kz3bZh for ; Mon, 19 Jul 2021 23:25:26 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=jM5jKJQz; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=hegdevasant@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=jM5jKJQz; dkim-atps=neutral Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4GT2Zd194Tz3bgk for ; Mon, 19 Jul 2021 23:22:32 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16JD5Iiu016075 for ; Mon, 19 Jul 2021 09:22:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=odD6eqOf1AaSz1Vpg36AUZQ6yWuAZQvIk936S+vnzx8=; b=jM5jKJQzRKDOH/LdWVd1m7srRQawV7HR6sppJ6a8wp4TQh/383lorHxTOdCPrYaOhtvc RCGFEmS6mZTqtqfnh0ueA9AflZqIj0EW7C0rcotdg5GCvDHQjaEwOQRPqecwuT1eWfqh s9bZXjeEq6w3nYK+ItUupfYhLOvERjzHWRmwGxsL5BVXwqMCYfumS4aT/uIdYDvU0pBS 8qyl3Z2sVKHdmJCthgVL30+7dI1fam+cRoTvEus8UAagMzjglu2k94UAW3UuZSuEsz/J L1PIoAEMl2FYKg5ZKohdNaCU/Hnjz9B6R4ntg74PqzRV67pR7D7ElGgs86dHATzE01Q6 sA== Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0b-001b2d01.pphosted.com with ESMTP id 39w7x4d2ef-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 19 Jul 2021 09:22:30 -0400 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16JDFRGc003894 for ; Mon, 19 Jul 2021 13:22:28 GMT Received: from b06avi18878370.portsmouth.uk.ibm.com (b06avi18878370.portsmouth.uk.ibm.com [9.149.26.194]) by ppma02fra.de.ibm.com with ESMTP id 39upu88cs6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 19 Jul 2021 13:22:28 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16JDK3bM17105156 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 19 Jul 2021 13:20:03 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6AA0FA4059; Mon, 19 Jul 2021 13:22:25 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C1CD4A4051; Mon, 19 Jul 2021 13:22:23 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:22:23 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:50:09 +0530 Message-Id: <20210719132012.150948-59-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: wpphP0VNEsI25J5bI_e2l-mnAgLWSLwJ X-Proofpoint-GUID: wpphP0VNEsI25J5bI_e2l-mnAgLWSLwJ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 clxscore=1015 bulkscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 58/61] P10 Cleanup special wakeup and xive stop api usage X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pratik R . Sampat" Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan Cleanup P9 code pending implementation for P10. P10 stop-api integration will be needed for STOP11 support only. STOP11 will be a restricted usage for testing core re-init on P10. Only stop0,2,3 will be available for general usage. Also, do not treat gated core with SPW done as error. Core gating bit is a software state updated by microcode, while SPWU done bit comes from hardware logic to indicate successful operation. Print a warning if the status bits are out of sync, but no need to fail the special wakeup operation. Signed-off-by: Vaidyanathan Srinivasan Signed-off-by: Pratik R. Sampat Signed-off-by: Vasant Hegde --- core/direct-controls.c | 34 +++++++++++++++++++++++++++------- hw/slw.c | 30 +++++++++--------------------- hw/xive2.c | 26 +------------------------- 3 files changed, 37 insertions(+), 53 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 879a537af..4795c19dc 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -600,15 +600,35 @@ static int p10_core_set_special_wakeup(struct cpu_thread *cpu) * CORE_GATED will be unset on a successful special * wakeup of the core which indicates that the core is * out of stop state. If CORE_GATED is still set then - * raise error. + * check SPWU register and raise error only if SPWU_DONE + * is not set, else print a warning and consider SPWU + * operation as successful. */ if (p10_core_is_gated(cpu)) { - /* Deassert spwu for this strange error */ - xscom_write(chip_id, spwu_addr, 0); - prlog(PR_ERR, "Failed special wakeup on %u:%u" - " core remains gated.\n", - chip_id, core_id); - return OPAL_HARDWARE; + if(xscom_read(chip_id, spwu_addr, &val)) { + prlog(PR_ERR, "Core %u:%u:" + " unable to read QME_SPWU_HYP\n", + chip_id, core_id); + return OPAL_HARDWARE; + } + if (val & P10_SPWU_DONE) { + /* + * If SPWU DONE bit is set then + * SPWU operation is complete + */ + prlog(PR_WARNING, "Special wakeup on " + "%u:%u: core remains gated while" + " SPWU_HYP DONE set\n", + chip_id, core_id); + return 0; + } + /* Deassert spwu for this strange error */ + xscom_write(chip_id, spwu_addr, 0); + prlog(PR_ERR, + "Failed special wakeup on %u:%u" + " core remains gated.\n", + chip_id, core_id); + return OPAL_HARDWARE; } else { return 0; } diff --git a/hw/slw.c b/hw/slw.c index e22d1bdde..52536db06 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -228,32 +228,20 @@ static bool slw_set_overrides_p10(struct proc_chip *chip, struct cpu_thread *c) int rc; uint32_t core = pir_to_core_id(c->pir); - /* Clear special wakeup bits that could hold power mgt */ - rc = xscom_write(chip->id, - XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), - 0); - if (rc) { - log_simple_error(&e_info(OPAL_RC_SLW_SET), - "SLW: Failed to write P10_QME_SPWU_HYP\n"); - return false; - } - /* Read back for debug */ + /* Special wakeup bits that could hold power mgt */ rc = xscom_read(chip->id, XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_HYP), &tmp); - if (tmp) + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_SET), + "SLW: Failed to read P10_QME_SPWU_HYP\n"); + return false; + } + if (tmp & P10_SPWU_REQ) prlog(PR_WARNING, - "SLW: core %d P10_QME_SPWU_HYP read 0x%016llx\n", - core, tmp); -#if 0 - rc = xscom_read(chip->id, - XSCOM_ADDR_P10_QME_CORE(core, P10_QME_SPWU_OTR), - &tmp); - if (tmp) - prlog(PR_WARNING, - "SLW: core %d P10_QME_SPWU_OTR read 0x%016llx\n", + "SLW: core %d P10_QME_SPWU_HYP requested 0x%016llx\n", core, tmp); -#endif + return true; } diff --git a/hw/xive2.c b/hw/xive2.c index b79635cc9..f559b0f9a 100644 --- a/hw/xive2.c +++ b/hw/xive2.c @@ -3022,34 +3022,10 @@ static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) void xive2_late_init(void) { - struct cpu_thread *c; - prlog(PR_INFO, "SLW: Configuring self-restore for NCU_SPEC_BAR\n"); - for_each_present_cpu(c) { - if(cpu_is_thread0(c)) { - struct proc_chip *chip = get_chip(c->chip_id); - struct xive *x = chip->xive; - uint64_t xa, val, rc; - xa = XSCOM_ADDR_P10_NCU(pir_to_core_id(c->pir), P10_NCU_SPEC_BAR); - val = (uint64_t)x->tm_base | P10_NCU_SPEC_BAR_ENABLE; - /* Bail out if wakeup engine has already failed */ - if ( wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { - prlog(PR_ERR, "XIVE p9_stop_api fail detected\n"); - break; - } /* - * TODO (p10): need P10 stop state engine + * TODO (p10): need P10 stop state engine and fix for STOP11 */ - rc = p9_stop_save_scom((void *)chip->homer_base, xa, val, - P9_STOP_SCOM_REPLACE, P9_STOP_SECTION_EQ_SCOM); - if (rc) { - xive_cpu_err(c, "p9_stop_api failed for NCU_SPEC_BAR rc=%lld\n", - rc); - wakeup_engine_state = WAKEUP_ENGINE_FAILED; - } - } - } - } static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c) {