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Mon, 19 Jul 2021 13:22:09 +0000 (GMT) Received: from hegdevasant.in.ibm.com (unknown [9.85.86.230]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 19 Jul 2021 13:22:09 +0000 (GMT) From: Vasant Hegde To: skiboot@lists.ozlabs.org Date: Mon, 19 Jul 2021 18:50:02 +0530 Message-Id: <20210719132012.150948-52-hegdevasant@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> References: <20210719132012.150948-1-hegdevasant@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jHRBPwlVA1nAuVwwuswRf-5UCVTDQmR0 X-Proofpoint-ORIG-GUID: jHRBPwlVA1nAuVwwuswRf-5UCVTDQmR0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-19_05:2021-07-19, 2021-07-19 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 spamscore=0 mlxlogscore=819 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107190076 Subject: [Skiboot] [PATCH 51/61] phb5: Add register inits specific to Gen5 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Frederic Barrat Update init sequence to take into account Gen5. Define default equlization settings if HDAT is not used. Signed-off-by: Frederic Barrat Signed-off-by: Vasant Hegde --- hw/phb4.c | 18 +++++++++++++----- include/phb4-regs.h | 6 ++++-- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index ef9f56d73..e3a60cf95 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -5388,8 +5388,12 @@ static void phb4_init_hw(struct phb4 *p) out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL1, be64_to_cpu(p->lane_eq[1])); out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL2, be64_to_cpu(p->lane_eq[2])); out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL3, be64_to_cpu(p->lane_eq[3])); - out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL20, be64_to_cpu(p->lane_eq[4])); - out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL21, be64_to_cpu(p->lane_eq[5])); + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL40, be64_to_cpu(p->lane_eq[4])); + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL41, be64_to_cpu(p->lane_eq[5])); + if (is_phb5()) { + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL50, be64_to_cpu(p->lane_eq[6])); + out_be64(p->regs + PHB_PCIE_LANE_EQ_CNTL51, be64_to_cpu(p->lane_eq[7])); + } } if (!p->lane_eq_en) { /* Read modify write and set to 2 bits */ @@ -5831,7 +5835,7 @@ static __be64 lane_eq_phb5_default[8] = { CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), - CPU_TO_BE64(0x4444444444444444UL), CPU_TO_BE64(0x4444444444444444UL), + CPU_TO_BE64(0x9999999999999999UL), CPU_TO_BE64(0x9999999999999999UL), }; static void phb4_create(struct dt_node *np) @@ -5843,7 +5847,7 @@ static void phb4_create(struct dt_node *np) struct dt_node *iplp; char *path; uint32_t irq_base, irq_flags; - int i; + int i, eq_reg_count; int chip_id; chip_id = dt_prop_get_u32(np, "ibm,chip-id"); @@ -5943,7 +5947,11 @@ static void phb4_create(struct dt_node *np) /* Check for lane equalization values from HB or HDAT */ p->lane_eq_en = true; p->lane_eq = dt_prop_get_def_size(np, "ibm,lane-eq", NULL, &lane_eq_len); - lane_eq_len_req = 6 * 8; + if (is_phb5()) + eq_reg_count = 8; + else + eq_reg_count = 6; + lane_eq_len_req = eq_reg_count * 8; if (p->lane_eq) { if (lane_eq_len < lane_eq_len_req) { PHBERR(p, "Device-tree has ibm,lane-eq too short: %ld" diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 99633e103..8ab78c377 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -295,8 +295,10 @@ #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 -#define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 -#define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 +#define PHB_PCIE_LANE_EQ_CNTL40 0x1AF0 +#define PHB_PCIE_LANE_EQ_CNTL41 0x1AF8 +#define PHB_PCIE_LANE_EQ_CNTL50 0x1B00 +#define PHB_PCIE_LANE_EQ_CNTL51 0x1B08 #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 #define PHB_PCIE_PDL_PHY_EQ_CNTL 0x1B38